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| PRELIMINARY DATA SHEET MICRONAS VDP 31xxB Video Processor Family Edition Sept. 25, 1998 6251-437-2PD MICRONAS VDP 31xxB Contents Page 5 6 7 7 7 7 7 7 7 7 7 9 10 10 11 11 11 11 11 11 12 12 13 13 13 14 15 15 15 16 17 17 17 17 18 18 18 18 19 19 19 19 Section 1. 1.1. 2. 2.1. 2.1.1. 2.1.2. 2.1.3. 2.1.4. 2.1.5. 2.1.6. 2.1.7. 2.2. 2.3. 2.3.1. 2.3.2. 2.3.3. 2.3.4. 2.3.5. 2.3.6. 2.3.7. 2.3.8. 2.3.9. 2.4. 2.5. 2.6. 2.7. 2.8. 2.8.1. 2.8.2. 2.8.3. 2.8.4. 2.8.5. 2.8.6. 2.8.7. 2.8.8. 2.8.9. 2.8.10. 2.8.11. 2.8.12. 2.8.13. 2.8.14. 2.8.15. Title Introduction VDP Applications Functional Description Analog Front-End Input Selector Clamping Automatic Gain Control Analog-to-Digital Converters ADC Range Digitally Controlled Clock Oscillator Analog Video Output Adaptive Comb Filter Color Decoder IF-Compensation Demodulator Chrominance Filter Frequency Demodulator Burst Detection Color Killer Operation PAL Compensation /1-H Comb Filter Luminance Notch Filter Skew Filtering Horizontal Scaler Black-Line Detector Test Pattern Generator Video Sync Processing Display Part Luma Contrast Adjustment Black Level Expander Dynamic Peaking Digital Brightness Adjustment Soft Limiter Chroma Input Chroma Interpolation Chroma Transient Improvement Inverse Matrix RGB Processing OSD Color Lookup Table Picture Frame Generator Priority Codec Scan Velocity Modulation Display Phase Shifter PRELIMINARY DATA SHEET 2 Micronas PRELIMINARY DATA SHEET VDP 31xxB Contents, continued Page 21 21 22 23 23 24 24 24 26 26 26 28 28 29 29 30 30 30 43 46 47 47 47 49 51 52 54 54 54 54 55 56 56 56 57 57 57 58 59 60 60 60 Section 2.9. 2.9.1. 2.9.2. 2.9.3. 2.9.4. 2.9.5. 2.9.6. 2.10. 2.11. 2.11.1. 2.11.2. 2.11.3. 2.11.4. 2.12. 2.13. 3. 3.1. 3.2. 3.2.1. 3.2.2. 4. 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.6.1. 4.6.2. 4.6.3. 4.6.4. 4.6.4.1. 4.6.4.2. 4.6.4.3. 4.6.4.4. 4.6.4.5. 4.6.4.6. 4.6.4.7. 4.6.4.8. 4.6.4.9. 4.6.4.10. 4.6.4.11. Title Analog Back End CRT Measurement and Control SCART Output Signal Average Beam Current Limiter Analog RGB Insertion Fast Blank Monitor Half Contrast Control IO Port Expander Synchronization and Deflection Deflection Processing Horizontal Phase Adjustment Vertical and East/West Deflection Protection Circuitry Reset Function Standby and Power-On Serial Interface I2C-Bus Interface Control and Status Registers Scaler Adjustment Calculation of Vertical and East-West Deflection Coefficients Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Pin Configuration Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Recommended Crystal Characteristics Characteristics 5 MHz Clock Output 20 MHz Clock Input/Output, External Clock Input (XTAL1) Reset Input, Test Input I2C-Bus Interface IO Port Expander Analog Video Inputs Analog Front-End and ADCs Picture Bus Input INTLC, Front Sync Output Main Sync Output Combined Sync Output Micronas 3 VDP 31xxB Contents, continued Page 61 61 61 61 62 62 62 63 64 66 66 67 72 Section 4.6.4.12. 4.6.4.13. 4.6.4.14. 4.6.4.15. 4.6.4.16. 4.6.4.17. 4.6.4.18. 4.6.4.19. 4.6.4.20. 4.6.4.21. 4.6.4.22. 5. 6. Title Horizontal Flyback Input Horizontal Drive Output Vertical Protection Input Vertical Safety Input Vertical and East/West Drive Output Sense A/D Converter Input Analog RGB and FB Inputs Half Contrast Switch Input Analog RGB Outputs, D/A Converters DAC Reference, Beam Current Safety Scan Velocity Modulation Output Application Circuit Data Sheet History PRELIMINARY DATA SHEET 4 Micronas PRELIMINARY DATA SHEET VDP 31xxB VPC 3200A Video Processor and DDP 3300A Display and Deflection Processor. Each member of the family contains the entire video, display, and deflection processing for 4:3 and 16:9 50/60 TV sets. Its performance and flexibility allow the user to standardize his product development. Hardware and software applications can profit from the modularity, as well as manufacturing, systems support, or maintenance. An overview of the VDP 31xxB video processor family is shown in Fig. 1-1. Video, Display, and Deflection Processor Release Notes: This data sheet describes functions and characteristics of the VDP 31xxB-C2. Revision bars indicate significant changes to the previous edition. 1. Introduction The VDP 31xxB is a Video IC family of high-quality single-chip video processors. Modular design and a submicron technology allow the economic integration of features in all classes of TV sets. The VDP 31xxB family is based on functional blocks contained in the two chips: Color Trans. Impr. 2H adapt. Comb Scan Vel. Mod. Prog. RGB Matrix Horizontal Scaler 1H Combfilter RGB Insertion n n n n n VDP 31xxB Family VDP 3104B VDP 3108B VDP 3112B VDP 3116B VDP 3120B n n n n n n n n n n n n n n n n n n n n n n Fig. 1-1: VDP 31xxB family overview VRT Tube Control n n n n n Color Bus XREF CIN VIN1 VIN2 VIN3 VIN4 VOUT Analog Frontend AGC, 2*8bit ADC 2H Adaptive Combfilter Color Decoder NTSC, PAL, SECAM Horizontal Scaler Panorama Mode Display Processor RGB Matrix, CLUT, Scan Veloc. Analog Backend 3*10bit DAC, Tube Control, RGB Switch RGB/FB IN1 RGB/FB IN2 Half Contrast RGB OUT SVM 20.25 MHz Clock Gen. DCO I2C Sync & Deflection Measurement ADC I2C H/V/EW Sense Fig. 1-2: Block diagram of the VDP 3120B Micronas 5 VDP 31xxB 1.1. VDP Applications As a member of the VDP 31xxB family, the VDP 3120B offers all video features necessary to design a state-ofthe-art TV set: Video Decoding - 4 composite inputs, 1 S-VHS input - composite video & sync output - integrated high-quality A/D converters - adaptive 2H comb filter Y/C separator - 1H NTSC comb filter - multistandard color decoder (1 crystal) - multistandard sync decoder - black line detector Miscellaneous Video Processing - horizontal scaling (0.25 to 4) - panorama vision - black level expander - dynamic peaking - soft limiter (gamma correction) - color transient improvement Deflection RGB Processing PRELIMINARY DATA SHEET - programmable RGB matrix - digital color bus interface - additional analog RGB / fast blank input - half-contrast switch - picture frame generator - scan velocity modulation output - high-performance H/V deflection - separate ADC for tube measurements - EHT compensation - one 20.25 MHz crystal, few external components - embedded RISC controller (80 MIPS) - I2C-Bus Interface - single 5 V power supply - submicron CMOS technology - 64-pin PSDIP package Video 1 Video 2 TPU 3040 DRAM CCU 300x VDP 3120B RGB H/VDefl. RGB 1 RGB 2 Audio MSP 3410 3 x Stereo DPL 3420 Dolby Surround Fig. 1-3: Full-feature TV set with VDP 3120B 6 Micronas PRELIMINARY DATA SHEET VDP 31xxB 2.1.3. Automatic Gain Control A digitally working automatic gain control adjusts the magnitude of the selected baseband by +6/-4.5 dB in 64 logarithmic steps to the optimal range of the ADC. The gain of the video input stage including the ADC is 213 steps/V with the AGC set to 0 dB. 2.1.4. Analog-to-Digital Converters 2. Functional Description 2.1. Analog Front-End This block provides the analog interfaces to all video inputs and mainly carries out analog-to digital conversion for the following digital video processing. A block diagram is given in Fig. 2-1. Most of the functional blocks in the front-end are digitally controlled (clamping, AGC, and clock-DCO). The control loops are closed by the Fast Processor (`FP') embedded in the decoder. Two ADCs are provided to digitize the input signals. Each converter runs with 20.25 MHz and has 8 bit resolution. An integrated bandgap circuit generates the required reference voltages for the converters. 2.1.5. ADC Range The ADC input range for the various input signals and the digital representation is given in Table 2-1 and Fig. 2-2. The corresponding output signal levels of the VDP 31xxB are also shown. 2.1.6. Digitally Controlled Clock Oscillator The clock generation is also a part of the analog front end. The crystal oscillator is controlled digitally by the control processor; the clock frequency can be adjusted within 150 ppm. 2.1.7. Analog Video Output The input signal of the Luma ADC is available at the analog video output pin. The signal at this pin must be buffered by a source follower. The output voltage is 2 V, thus the signal can be used to drive a 75 W line. The magnitude is adjusted with an AGC in 8 steps together with the main AGC. 2.1.1. Input Selector Up to five analog inputs can be connected. Four inputs are for input of composite video or S-VHS luma signal. These inputs are clamped to the sync back porch and are amplified by a variable gain amplifier. One input is for connection of S-VHS carrier-chrominance signal. This input is internally biased and has a fixed gain amplifier. 2.1.2. Clamping The composite video input signals are AC coupled to the IC. The clamping voltage is stored on the coupling capacitors and is generated by digitally controlled current sources. The clamping level is the back porch of the video signal. S-VHS chroma is also AC coupled. The input pin is internally biased to the center of the ADC input range. Analog Video Output CVBS/Y VIN4 CVBS/Y CVBS/Y VIN3 input mux VIN2 clamp 3 AGC +6/-4.5 dB ADC gain digital CVBS or Luma CVBS/Y/C VIN1 Chroma CIN bias ADC digital Chroma system clocks reference generation frequency DVCO 150 ppm 20.25 MHz Fig. 2-1: Analog front-end Micronas 7 VDP 31xxB Table 2-1: ADC input range for PAL input signal and corresponding signal ranges Signal Input Level [mVpp] PRELIMINARY DATA SHEET ADC Range [steps] 252 213 149 64 68 YCrCb Internal Range [steps] - - 224 - 16 - 128112 12884 128 -6 dB CVBS 100% CVBS 75% CVBS video (luma) sync height clamp level Chroma burst 100% Chroma 75% Chroma bias level 667 500 350 150 0 dB 1333 1000 700 300 +4.5 dB 2238 1679 1175 504 300 890 670 64 190 143 128 CVBS/Y Chroma headroom = 56 steps = 2.1 dB 228 192 217 192 white video = 100 IRE 128 128 black = clamp level 68 32 0 80 sync = 41 IRE lower headroom = 4 steps = 0.2 dB Fig. 2-2: ADC ranges for CVBS/Luma and Chroma, PAL input signal 8 IIIIIIII IIIIIIII 32 IIIIIIII IIIIIIII 100% Chroma 75% Chroma burst IIIIIIIII IIIIIIIII IIIIIIIII 255 upper headroom = 38 steps = 1.4 dB = 25 IRE Micronas PRELIMINARY DATA SHEET VDP 31xxB Two parameters (KY, KC) set the global gain of luma and chroma comb separately; these values directly weigh the adaption algorithm output. In this way, it is possible to obtain a luma/chroma separation ranging from standard notch/bandpass to full comb decoding. The parameter KB allows to choose between the two proposed comb booster modes. This so-called feature widely improves vertical high to low frequency transitions areas, the typical example being a multiburst to dc change. For KB=0, this improvement is kept moderate, whereas, in case of KB=1, it is maximum, but the risk to increase the "hanging dots" amount for some given color transitions is higher. Using the default setting, the comb filter has separate luma and chroma decision algorithms; it is however possible to switch the chroma comb factor to the current luma adaption output by setting CC to 1. Another interesting feature is the programmable limitation of the luma comb amount; proper limitation, associated to adequate luma peaking, gives rise to an enhanced 2-D resolution homogeneity. This limitation is set by the parameter CLIM, ranging from 0 (no limitation) to 31 (max. limitation). The DAA parameter (1:off , 0:on) is used to disable/enable a very efficient built-in "rain effect" suppressor; many comb filters show this side effect which gives some vertical correlation to a 2-D uniform random area, due to the vertical filtering. This unnatural-looking phenomenon is mostly visible on tuner images, since they are always corrupted by some noise; and this looks like rain. 2.2. Adaptive Comb Filter The adaptive comb filter is used for high-quality luminance/chrominance separation for PAL or NTSC signals. The comb filter improves the luminance resolution (bandwidth) and reduces interferences like cross-luminance and cross-color artifacts. The adaptive algorithm can eliminate most of the mentioned errors without introducing new artifacts or noise. A block diagram of the comb filter is shown in Fig. 2-3. The filter uses two line delays to process the information of three adjacent video lines. To have a fixed phase relationship of the color subcarrier in the three channels, the system clock (20.25 MHz) is fractionally locked to the color subcarrier. This allows the processing of all color standards and substandards using a single crystal frequency. The CVBS signal in the three channels is filtered at the subcarrier frequency by a set of bandpass / notch filters. The output of the three channels is used by the adaption logic to select the weighting that is used to reconstruct the luminance/chrominance signal from the 4 bandpass/ notch filter signals. By using soft mixing of the 4 signals switching artifacts of the adaption algorithm are completely suppressed. The comb filter uses the middle line as reference, therefore, the comb filter delay is one line. If the comb filter is switched off, the delay lines are used to pass the luma/ chroma signals from the A/D converters to the luma/ chroma outputs. Thus, the comb filter delay is always one line. Various parameters of the comb filter are adjustable, hence giving to the user the ability to adjust his own desired picture quality. CVBS Input 1 H Line Delay Bandpass/ Notch Filter Luma / Chroma Mixers Adaption Logic Bandpass Filter Luma Output Chroma Output 1 H Line Delay Chroma Input Bandpass Filter Fig. 2-3: Block diagram of the adaptive comb filter Micronas 9 VDP 31xxB 2.3. Color Decoder In this block, the standard luma/chroma separation and multi-standard color demodulation is carried out. The color demodulation uses an asynchronous clock, thus allowing a unified architecture for all color standards. A block diagram of the color decoder is shown in Fig. 2-5. The luma as well as the chroma processing, is shown here. The color decoder provides also some special modes, e.g. wide band chroma format which is intended for S-VHS wide bandwidth chroma. If the adaptive comb filter is used for luma chroma separation, the color decoder uses the S-VHS mode processing. The output of the color decoder is YCrCb in a 4:2:2 format. PRELIMINARY DATA SHEET 2.3.1. IF-Compensation With off-air or mistuned reception, any attenuation at higher frequencies or asymmetry around the color subcarrier is compensated. Four different settings of the IFcompensation are possible: - flat (no compensation) - 6 dB /octave - 12 dB /octave - 10 dB/MHz The last setting gives a very large boost to high frequencies. It is provided for SECAM signals that are decoded using a SAW filter specified originally for the PAL standard. Fig. 2-4: Frequency response of chroma IF-compensation Luma / CVBS Notch Filter Luma MUX 1 H Delay Cross-Switch Chroma / CrCb ACC MUX IF Compensation DC-Reject MIXER Lowpass Filter Phase/Freq Demodulator Chroma Color-PLL / Color-ACC Fig. 2-5: Color decoder 10 Micronas PRELIMINARY DATA SHEET VDP 31xxB 2.3.4. Frequency Demodulator The frequency demodulator for demodulating the SECAM signal is implemented as a CORDIC-structure. It calculates the phase and magnitude of the quadrature components by coordinate rotation. The phase output of the CORDIC processor is differentiated to obtain the demodulated frequency. After the deemphasis filter, the Dr and Db signals are scaled to standard CrCb amplitudes and fed to the crossoverswitch. 2.3.5. Burst Detection In the PAL/NTSC-system the burst is the reference for the color signal. The phase and magnitude outputs of the CORDIC are gated with the color key and used for controlling the phase-lock-loop (APC) of the demodulator and the automatic color control (ACC) in PAL/NTSC. The ACC has a control range of +30 ... -6 dB. For SECAM decoding, the frequency of the burst is measured. Thus, the current chroma carrier frequency can be identified and is used to control the SECAM processing. The burst measurements also control the color killer operation; they can be used for automatic standard detection as well. 2.3.6. Color Killer Operation The color killer uses the burst-phase / burst-frequency measurement to identify a PAL/NTSC or SECAM color signal. For PAL/NTSC, the color is switched off (killed) as long as the color subcarrier PLL is not locked. For SECAM, the killer is controlled by the toggle of the burst frequency. The burst amplitude measurement is used to switch-off the color if the burst amplitude is below a programmable threshold. Thus, color will be killed for very noisy signals. The color amplitude killer has a programmable hysteresis. 2.3.7. PAL Compensation / 1-H Comb Filter 2.3.2. Demodulator The entire signal (which might still contain luma) is now quadrature-mixed to the baseband. The mixing frequency is equal to the subcarrier for PAL and NTSC, thus achieving the chroma demodulation. For SECAM, the mixing frequency is 4.286 MHz giving the quadrature baseband components of the FM modulated chroma. After the mixer, a lowpass filter selects the chroma components; a downsampling stage converts the color difference signals to a multiplexed half rate data stream. The subcarrier frequency in the demodulator is generated by direct digital synthesis; therefore, substandards such as PAL 3.58 or NTSC 4.43 can also be demodulated. 2.3.3. Chrominance Filter The demodulation is followed by a lowpass filter for the color difference signals for PAL/NTSC. SECAM requires a modified lowpass function with bell-filter characteristic. At the output of the lowpass filter, all luma information is eliminated. The lowpass filters are calculated in time multiplex for the two color signals. Three bandwidth settings (narrow, normal, broad) are available for each standard. For PAL/ NTSC, a wide band chroma filter can be selected. This filter is intended for high bandwidth chroma signals, e.g. a nonstandard wide bandwidth S-VHS signal. PAL/NTSC The color decoder uses one fully integrated delay line. Only active video is stored. The delay line application depends on the color standard: - NTSC: - PAL: 1-H comb filter or color compensation color compensation - SECAM: crossover-switch In the NTSC compensated mode, Fig. 2-7 c), the color signal is averaged for two adjacent lines. Thus, crosscolor distortion and chroma noise is reduced. In the NTSC combfilter mode, Fig. 2-7 d), the delay line is in the composite signal path, thus allowing reduction of 11 SECAM Fig. 2-6: Frequency response of chroma filters Micronas VDP 31xxB cross-color components, as well as cross-luminance. The loss of vertical resolution in the luminance channel is compensated by adding the vertical detail signal with removed color information. PRELIMINARY DATA SHEET 2.3.8. Luminance Notch Filter If a composite video signal is applied, the color information is suppressed by a programmable notch filter. The position of the filter center frequency depends on the subcarrier frequency for PAL/NTSC. For SECAM, the notch is directly controlled by the chroma carrier frequency. This considerably reduces the cross-luminance. The frequency responses for all three systems are shown in Fig. 2-10. 10 dB CVBS 8 Notch filter Chroma Process. Y CrC b Luma 8 Y Chroma Process. Chroma 8 CrC b a) conventional CVBS 8 Notch filter b) S-VHS Y 0 -10 Chroma Process. 1H Delay CrC b -20 c) compensated Notch filter 1H Delay -30 CVBS 8 Y -40 0 2 4 6 8 10 MHz PAL/NTSC notch filter dB Chroma Process. CrC b 10 0 d) comb filter -10 Fig. 2-7: NTSC color decoding options -20 -30 CVBS 8 Notch filter Y -40 0 2 4 6 8 10 MHz SECAM notch filter Chroma Process. 1H Delay CrC b a) conventional Luma 8 Fig. 2-10: Frequency responses of the luma notch filter for PAL, NTSC, and SECAM Y 2.3.9. Skew Filtering The system clock is free-running and not locked to the TV line frequency. Therefore, the ADC sampling pattern is not orthogonal. The decoded YCrCb signals are converted to an orthogonal sampling raster by the skew filters, which are part of the scaler block. The skew filters allow the application of a group delay to the input signals without introducing waveform or frequency response distortion. Chroma 8 Chroma Process. 1H Delay CrC b b) S-VHS Fig. 2-8: PAL color decoding options CVBS 8 Notch filter Y Chroma Process. 1H Delay MUX CrC b Fig. 2-9: SECAM color decoding The amount of phase shift of this filter is controlled by the horizontal PLL1. The accuracy of the filters is 1/32 clocks for luminance and 1/4 clocks for chroma. Thus the 4:2:2 YCrCb data is in an orthogonal pixel format even in the case of nonstandard input signals such as VCR. Micronas 12 PRELIMINARY DATA SHEET VDP 31xxB 2.5. Black-Line Detector In case of a letterbox format input video, e.g. Cinemascope, PAL+ etc., black areas at the upper and lower part of the picture are visible. It is suitable to remove or reduce these areas by a vertical zoom and/or shift operation. The VDP 31xxB supports this feature by a letterbox detector. The circuitry detects black video lines by measuring the signal amplitude during active video. For every field the number of black lines at the upper and lower part of the picture are measured, compared to the previous measurement and the minima are stored in the I2C-register BLKLIN. To adjust the picture amplitude, the external controller reads this register, calculates the vertical scaling coefficient and transfers the new settings, e.g. vertical sawtooth parameters, horizontal scaling coefficient etc., to the VDP. Letterbox signals containing logos on the left or right side of the black areas are processed as black lines, while subtitles, inserted in the black areas, are processed as non-black lines. Therefore the subtitles are visible on the screen. To suppress the subtitles, the vertical zoom coefficient is calculated by selecting the larger number of black lines only. Dark video scenes with a low contrast level compared to the letterbox area are indicated by the BLKPIC bit. 2.4. Horizontal Scaler The 4:2:2 YCrCb signal from the color decoder is processed by the horizontal scaler. The scaler block allows a linear or nonlinear horizontal scaling of the input video signal in the range of 0.25 to 4. Nonlinear scaling, also called "panorama vision", provides a geometrical distortion of the input picture. It is used to fit a picture with 4:3 format on a 16:9 screen by stretching the picture geometry at the borders. Also, the inverse effect can be produced by the scaler. A summary of scaler modes is given in Table 2-2. The scaler contains a programmable decimation filter, a 1-line FIFO memory, and a programmable interpolation filter. The scaler input filter is also used for pixel skew correction, see 2.3.9. The decimator/interpolator structure allows optimal use of the FIFO memory. The controlling of the scaler is done by the internal Fast Processor. Table 2-2: Scaler modes Mode Compression 4:3 16:9 Panorama 4:3 16:9 Zoom 4:3 4:3 Scale Factor 0.75 linear nonlinear compr 1.33 linear Description 4:3 source displayed on a 16:9 tube, with side panels 4:3 source displayed on a 16:9 tube, Borders distorted Letterbox source (PAL+) displayed on a 4:3 tube, vertical overscan with cropping of side panels Letterbox source (PAL+) displayed on a 4:3 tube, vertical overscan, borders distorted, no cropping 2.6. Test Pattern Generator The YCrCb outputs of the front-end can be switched to a test mode where YCrCb data are generated digitally in the VDP 31xxB. Test patterns include luma/chroma ramps, flat fields and a pseudo color bar pattern. Panorama 4:3 4:3 nonlinear zoom Micronas 13 VDP 31xxB 2.7. Video Sync Processing Fig. 2-11 shows a block diagram of the front-end sync processing. To extract the sync information from the video signal, a linear phase lowpass filter eliminates all noise and video contents above 1 MHz. The sync is separated by a slicer; the sync phase is measured. A variable window can be selected to improve the noise immunity of the slicer. The phase comparator measures the falling edge of sync, as well as the integrated sync pulse. The sync phase error is filtered by a phase-locked loop that is computed by the FP. All timing in the front-end is derived from a counter that is part of this PLL, and it thus counts synchronously to the video signal. A separate hardware block measures the signal back porch and also allows gathering the maximum/minimum of the video signal. This information is processed by the FP and used for gain control and clamping. PRELIMINARY DATA SHEET For vertical sync separation, the sliced video signal is integrated. The FP uses the integrator value to derive vertical sync and field information. The information extracted by the video sync processing is multiplexed onto the hardware front sync signal (FSY) and is distributed to the rest of the video processing system. The format of the front sync signal is given in Fig. 2-12. The data for the vertical deflection, the sawtooth, and the East-West correction signal is calculated by the VDP 31xxB. The data is buffered in a FIFO and transferred to the back-end by a single wire interface. Frequency and phase characteristics of the analog video signal are derived from PLL1. The results are fed to the scaler unit for data interpolation and orthogonalization and to the clock synthesizer for line-locked clock generation. Horizontal and vertical syncs are latched with the line-locked clock. PLL1 lowpass 1 MHz & syncslicer video input front-end timing clamp & signal meas. clamping, colorkey, FIFO_write clock synthesizer syncs clock H/V syncs horizontal sync separation phase comparator & lowpass counter front sync generator front sync skew vblank field vertical sync separation Sawtooth Parabola Calculation FIFO vertical serial data vertical E/W sawtooth Fig. 2-11: Sync separation block diagram F1 input analog video skew LSB skew not MSB used F V F0 reserved (not in scale) F0 F1 V: vertical sync 0 = off Parity 1 = on F: field # 0 = field 1 1 = field 2 FSY Fig. 2-12: Front sync format 14 Micronas PRELIMINARY DATA SHEET VDP 31xxB 2.8.2. Black Level Expander The black level expander enhances the contrast of the picture. Therefore the luminance signal is modified with an adjustable, non-linear function. Dark areas of the picture are changed to black, while bright areas remain unchanged. The advantage of this black level expander is that the black expansion is performed only if it will be most noticeable to the viewer. The black level expander works adaptively. Depending on the measured amplitudes `Lmin' and `Lmax' of the lowpass-filtered luminance and an adjustable coefficient BTLT, a tilt point `Lt' is established by Lt = Lmin + BTLT (Lmax - Lmin). Above this value there is no expansion, while all luminance values below this point are expanded according to: Lout = Lin + BAM (Lin - Lt) A second threshold, Ltr, can be programmed, above which there is no expansion. The characteristics of the black level expander are shown in Fig. 2-13 and Fig. 2-14. The tilt point Lt is a function of the dynamic range of the video signal. Thus, the black level expansion is only performed when the video signal has a large dynamic range. Otherwise, the expansion to black is zero. This allows the correction of the characteristics of the picture tube. 2.8. Display Part In the display part the conversion from digital YCrCb to analog RGB is carried out. A block diagram is shown in Figure 2-20. In the luminance processing path, contrast and brightness adjustments and a variety of features, such as black level expansion, dynamic peaking and soft limiting, are provided. In the chrominance path, the CrCb signals are converted to 20.25 MHz sampling rate and filtered by a color transient improvement circuit. The YCrCb signals are converted by a programmable matrix to RGB color space. The display processor provides separate control settings for two pictures, i.e. different coefficients for a `main' and a `side' picture. The digital OSD insertion circuit allows the insertion of a 5-bit OSD signal. The color space for this signal is controlled by a partially programmable color look-up table (CLUT) and contrast adjustment. The OSD signals and the display clock are synchronized to the horizontal flyback. For the display clock, a gate delay phase shifter is used. In the analog backend, three 10-bit digital-to-analog converters provide the analog output signals. 2.8.1. Luma Contrast Adjustment The contrast of the luminance signal can be adjusted by multiplication with a 6-bit contrast value. The contrast value corresponds to a gain factor from 0 to 2, where the value 32 is equivalent to a gain of 1. The contrast can be adjusted separately for main picture and side picture. a) Lmax Lt Lmin Lout Ltr Lt BAM BTLT Lmin Lmax b) Lt Ltr BTHR Lin Fig. 2-13: Characteristics of the black level expander Fig. 2-14: Black-level-expansion a) luminance input b) luminance input and output 15 Micronas VDP 31xxB 2.8.3. Dynamic Peaking Especially with decoded composite signals and notch filter luminance separation, as input signals, it is necessary to improve the luminance frequency characteristics. With transparent, high-bandwidth signals, it is sometimes desirable to soften the image. In the VDP 31xxB, the luma response is improved by `dynamic' peaking. The algorithm has been optimized regarding step and frequency response. It adapts to the amplitude of the high frequency part. Small AC amplitudes are processed, while large AC amplitudes stay nearly unmodified. The dynamic range can be adjusted from *14 to )14 dB for small high frequency signals. There is separate adjustment for signal overshoot and for signal undershoot. For large signals, the dynamic range is limited by a non-linear function that does not create any visible alias components. The peaking can be switched over to "softening" by inverting the peaking term by software. PRELIMINARY DATA SHEET The center frequency of the peaking filter is switchable from 2.5 MHz to 3.2 MHz. For S-VHS and for notch filter color decoding, the total system frequency responses for both PAL and NTSC are shown in figure 2-16. Transients, produced by the dynamic peaking when switching video source signals, can be suppressed via the priority bus. dB 20 15 10 5 0 -5 -10 -15 -20 0 2 4 6 8 10 MHz Fig. 2-15: Dynamic peaking frequency response dB 20 15 10 5 0 -5 -10 -15 -20 0 dB 20 15 10 5 0 -5 -10 -15 -20 0 2 4 6 8 10 MHz 20 2 4 6 8 10 MHz 20 15 dB CF= 2.5 MHz CF= 3.2 MHz 10 5 S-VHS 0 -5 -10 -15 -20 0 dB 2 4 6 8 10 MHz CF= 3.2 MHz 15 10 5 CF= 2.5 MHz PAL/SECAM 0 -5 -10 -15 -20 0 dB 20 2 4 6 8 10 MHz dB 20 15 10 5 0 -5 -10 -15 -20 0 2 4 6 8 10 MHz CF= 3.2 MHz 15 10 5 CF= 2.5 MHz NTSC 0 -5 -10 -15 -20 0 2 4 6 8 10 MHz Fig. 2-16: Total frequency response for peaking filter and S-VHS, PAL, NTSC 16 Micronas PRELIMINARY DATA SHEET VDP 31xxB signal itself. Therefore, the gain is adjustable from 16/16 to 1/16, when the slope value varies from 0 to 15. The tilt value can be adjusted from 0 to 511. Part 2 has the same characteristics as part 1. The subtracting part is also relative to the input signal, so the total differential gain will become negative if the sum of slope 1 and slope 2 is greater than 16 and the input signal is above the both tilt values (see characteristics). Finally, the output signal of the soft limiter will be clipped by a hard limiter adjustable from 256 to 511. 2.8.6. Chroma Input 2.8.4. Digital Brightness Adjustment The DC-level of the luminance signal can be adjusted by adding an 8-bit number in the luminance signal path in front of the softlimiter. With a contrast adjustment of 32 (gain+1) the signal can be shifted by "100%. After the brightness addition, the negative going signals are limited to zero. It is desirable to keep a small positive offset with the signal to prevent undershoots produced by the peaking from being cut. The digital brightness adjustment is separate for main and side picture. 2.8.5. Soft Limiter The dynamic range of the processed luma signal must be limited to prevent the CRT from overload. An appropriate headroom for contrast, peaking and brightness can be adjusted by the TV manufacturer according to the CRT characteristics. All signals above this limit will be `soft'-clipped. A characteristic diagram of the soft limiter is shown in Fig. 2-17. The total limiter consists of three parts: Part 1 includes adjustable tilt point and gain. The gain before the tilt value is 1. Above the tilt value, a part (0...15/16) of the input signal is subtracted from the input The chroma input signal is a multiplexed CR and CB signal in 8-bit binary offset code. It can be switched between normal and inverted signal and between two's complement and binary offset code. The delay in respect to the luminance input can be adjusted in 5 steps within a range of "2 clock periods. 2.8.7. Chroma Interpolation A linear phase interpolator is used to convert the chroma sampling rate from 10.125 MHz (4:2:2) to 20.25 MHz (4:4:4). All further processing is carried out at the full sampling rate. Output 511 Part 1 Part 2 0 2 4 6 8 10 12 14 slope 2 [0...15] Hard limiter 400 300 200 slope 1 [0...15] 0 2 4 6 8 10 12 14 Calculation Example for the Softlimiter Input Amplitude. (The real signal processing in the limiter is 2 bit more than described here) Y Input Black Level Contrast Dig. Brightness BLE Peaking 16...235 (ITUR) 16 (constant) 63 20 off off range= 256...511 100 tilt 1 [ 0...511] 0 0 100 200 300 400 500 600 700 800 900 tilt 2 [0...511] Limiter input signal: (Yin-Black Level)*Contr./32 + Brightn. (235-16) * 63/32 + 20 = 451 Limiter Input 1023 Fig. 2-17: Characteristic of soft limiter a and b and hard limiter Micronas 17 VDP 31xxB 2.8.8. Chroma Transient Improvement The intention of this block is to enhance the chroma resolution. A correction signal is calculated by differentiation of the color difference signals. The differentiation can be selected according to the signal bandwidth, e.g. for PAL/NTSC/SECAM or digital component signals, respectively. The amplitude of the correction signal is adjustable. Small noise amplitudes in the correction signal are suppressed by an adjustable coring circuit. To eliminate `wrong colors', which are caused by over and undershoots at the chroma transition, the sharpened chroma signals are limited to a proper value automatically. a) PRELIMINARY DATA SHEET 2.8.9. Inverse Matrix A 6-multiplier matrix transcodes the Cr and Cb signals to R-Y, B-Y, and G-Y. The multipliers are also used to adjust color saturation in the range of 0 to 2. The coefficients are signed and have a resolution of 9 bits. There are separate matrix coefficients for main and side pictures. The matrix computes: R-Y+MR1*Cb)MR2*Cr G-Y+MG1*Cb)MG2*Cr B-Y+MB1*Cb)MB2*Cr The initialization values for the matrix are computed from the standard ITUR (CCIR) matrix: R G+ B 1 0 1.402 1 * 0.345 * 0.713 1 1.773 0 Y Cb Cr Cr in Cb in For a contrast setting of CTM+32, the matrix values are scaled by a factor of 64, see also table 3-1. t b) 2.8.10. RGB Processing After adding the post-processed luma, the digital RGB signals are limited to 10 bits. Three multipliers are used to digitally adjust the white drive. Using the same multipliers an average beam current limiter is implemented. See also section 2.9.1. `CRT Measurement and Control'. 2.8.11. OSD Color Lookup Table The VDP 31xxB has five input lines for an OSD signal. This signal forms a 5-bit address for a color look-up table (CLUT). The CLUT is a memory with 32 words where each word holds a RGB value. Bits 0 to 3 (bit 4+0) form the addresses for the ROM part of the OSD, which generates full RGB signals (bit 0 to 2) and half-contrast RGB signals (bit 3). Bit 4 addresses the RAM part of the OSD with 16 freely programmable colors, addressable with bit 0 to 3. The programming is done via the I2C-bus. The amplitude of the CLUT output signals can be adjusted separately for R, G and B via the I2C-bus. The switchover between video RGB and OSD RGB is done via the Priority bus. Ampl. t c) Cr out Cb out t a) Cr Cb input of DTI b) Cr Cb input)Correction signal c) sharpened and limited Cr Cb Fig. 2-18: Digital Color Transient Improvement 18 Micronas PRELIMINARY DATA SHEET VDP 31xxB 2.8.14. Scan Velocity Modulation The RGB input signal of the SVM is converted to Y in a simple matrix. Then the Y signal is differentiated by a filter of the transfer function 1-Z-N, where N is programmable from 1 to 6. With a coring, some noise can be suppressed. This is followed by a gain adjustment and an adjustable limiter. The analog output signal is generated by an 8-bit D/A converter. The signal delay can be adjusted by 3.5 clocks in halfclock steps. For the gain and filter adjustment there are two parameter sets. The switching between these two sets is done with the same RGB switch signal that is used for switching between video-RGB and OSD-RGB for the RGB outputs. (See Fig. 2-19). 2.8.15. Display Phase Shifter 2.8.12. Picture Frame Generator When the picture does not fill the total screen (height or width too small) it is surrounded with black areas. These areas (and more) can be colored with the picture frame generator. This is done by switching over the RGB signal from the matrix to the signal from the OSD color look-up table. The width of each area (left, right, upper, lower) can be adjusted separately. The generator starts on the right, respectively lower side of the screen and stops on the left, respectively upper side of the screen. This means, it runs during horizontal, respectively vertical flyback. The color of the complete border can be stored in the programmable OSD color look-up table in a separate address. The format is 3 4 bit RGB. The contrast can be adjusted separately. The picture frame generator includes a priority master circuit. Its priority is programmable and the border is generated only if the priority is higher than the priority at the PRIO bus. Therefore the border can be underlay or overlay depending on the picture source. 2.8.13. Priority Codec The priority decoder has three input lines for up to eight priorities. The highest priority is all three lines at low level. A 5-bit information is attached to each priority (see table 3-1 `Priority Bus'). These bits are programmable via the I2C-bus and have the following meanings: - one of two contrast, brightness and matrix values for main and side picture - RGB from video signal or color look-up table - disable/enable black level expander - disable/enable peaking transient suppression when signal is switched - disable/enable analog fast blank input 1 - disable/enable analog fast blank input 2 A phase shifter is used to partially compensate the phase differences between the video source and the flyback signal. By using the described clock system, this phase shifter works with an accuracy of approximately 1 ns. It has a range of 1 clock period which is equivalent to 24.7 ns at 20.25 MHz. The large amount of phase shift (full clock periods) is realized in the front-end circuit. R G B N1 N2 Coring Gain1 Gain2 RGB Switch Limit Delay Matrix and Shaping Modulation Notch Differentiator 1-Z-Nx Coring adjustment Gain adjustment Limiter Delay adjustment D/A Converter Output Fig. 2-19: SVM block diagram Micronas 19 20 Micronas VDP 31xxB Fig. 2-20: Digital back-end dig. Y in 8 5 contrast brightness + offset whitedrive measurement dynamic peaking clock prio softlimiter luma insert for CRTmeasurement Picture Frame Generator whitedrive R x beamcurr. lim. display & clock control horizontal flyback CLUT, Contrast dig. OSD in black level expander 8 blanking for CRTmeasurement Y Matrix R' Phase Shift 0...1 clock R whitedrive G x beamcurr. lim. dig. Rout 10 prio Cr dig. CrCb in DTI (Cr) Interpol 4:4:4 DTI (Cb) Matrix G' Phase Shift 0...1 clock G whitedrive B x beamcurr. lim. dig. Gout 10 Cb PRIO in 3 side picture PRIO decoder select coefficients main picture Matrix B' Phase Shift 0...1 clock B dig. Bout PRELIMINARY DATA SHEET 10 Scan Velocity Modulation Matrix saturation SVMout PRELIMINARY DATA SHEET VDP 31xxB Cutoff and white drive current measurement are carried out during the vertical blanking interval. They always use the small bandwidth setting. The current range for the cutoff measurement is set by connecting a sense resistor to the MADC input. For the whitedrive measurement, the range is set by using another sense resistor and the range select switch 2 output pin (RSW2). During the active picture, the minimum and maximum beam current is measured. The measurement range can be set by using the range select switch 1 pin (RSW1) as shown in Fig. 2-21 and Fig. 2-22. The timing window of this measurement is programmable. The intention is to automatically detect letterbox transmission or to measure the actual beam current. All control loops are closed via the external control microprocessor. beam current A D MADC SENSE 2.9. Analog Back End The digital RGB signals are converted to analog RGBs using three video digital to analog converters (DAC) with 10-bit resolution. An analog brightness value is provided by three additional DACs. The adjustment range is 40% of the full RGB range. Controlling the whitedrive/analog brightness and also the external contrast and brightness adjustments is done via the Fast Processor, located in the front-end. Control of the cutoff DACs is via I2C-bus registers. Finally cutoff and blanking values are added to the RGB signals. Cutoff (dark current) is provided by three 9-bit DACs. The adjustment range is 60% of full scale RGB range. The analog RGB-outputs are current outputs with current-sink characteristics. The maximum current drawn by the output stage is obtained with peak white RGB. An external half contrast signal can be used to reduce the output current of the RGB outputs to 50%. 2.9.1. CRT Measurement and Control The display processor is equipped with an 8-bit PDMADC for all measuring purposes. The ADC is connected to the sense input pin, the input range is 0 to 1.5V. The bandwidth of the PDM filter can be selected; it is 40/80 kHz for small/large bandwidth setting. The input impedance is more than 1 M. RSW1 RSW2 R2 R3 R1 Fig. 2-21: MADC Range Switches CR + IBRM + WDRV*WDR CR + IBRM white drive cutoff R R black ultra black R cutoff G CG + IBRM G cutoff B CB + IBRM B active measurement resistor R1oR2oR3 RSW1=on, RSW2=on PICTURE MEAS. PMSO R1 R1oR3 RSW2 =on R1oR2oR3 RSW1=on, RSW2=on PICTURE MEAS. TUBE MEASUREMENT TML PMST Lines Fig. 2-22: MADC Measurement Timing Micronas 21 VDP 31xxB In each field two sets of measurements can be taken: a) The picture tube measurement returns results for - cutoff R - cutoff G - cutoff B - white drive R or G or B (sequentially) b) The picture measurement returns data on - active picture maximum current - active picture minimum current active video field 1/ 2 PRELIMINARY DATA SHEET The vertical timing for the picture measurement is programmable, and may even be a single line. Also the signal bandwidth is switchable for the picture measurement. Two horizontal windows are available for the picture measurement. The large window is active for the entire active line. Tube measurement is always carried out with the small window. Measurement windows for picture and tube measurement are shown in Figure 2-23. tube measurement picture meas. start picture meas. end Fig. 2-23: Windows for tube and picture measurements 2.9.2. SCART Output Signal The RGB output of the VDP 31xxB can also be used to drive a SCART output. In the case of the SCART signal, the parameter CLMPR (clamping reference) has to be set to 1. Then, during blanking, the RGB outputs are automatically set to 50% of the maximum brightness. The DC offset values can be adjusted with the cutoff parameters CR, CG, and CB. The amplitudes can be adjusted with the drive parameters WDR, WDG, and WDB. The picture measurement must be enabled by the control microprocessor after reading the min./max. result registers. If a `1' is written into bit 2 in subaddress 25, the measurement runs for one field. For the next measurement a `1' has to be written again. The measurement is always started at the beginning of active video. 22 IIIIIIIII III III small window for tube measurement (cutoff, white drive) large window for active picture The tube measurement is automatically started when the cutoff blue result register is read. Cutoff control for RGB requires one field only while a complete white-drive control requires three fields. If the measurement mode is set to `offset check', a measurement cycle is run with the cutoff/whitedrive signals set to zero. This allows to compensate the MADC offset as well as input the leakage currents. During cutoff and whitedrive measurements, the average beam current limiter function (ref. 2.9.3.) is switched off and a programmable value is used for the brightness setting. The start line of the tube measurement can be programmed via I2C-bus, the first line used for the measurement, i.e. measurement of cutoff red, is 2 lines after the programmed start line. Micronas PRELIMINARY DATA SHEET VDP 31xxB 2.9.4. Analog RGB Insertion The VDP 31xxB allows insertion of 2 external analog RGB signals. Each RGB signal is key-clamped and inserted into the main RGB by the fast blank switch. The selected external RGB input is virtually handled as a priority bus signal. Thus, it can be overlaid or underlaid to the digital picture. The external RGB signals can be adjusted independently as regards DC-level (brightness) and magnitude (contrast). Which analog RGB input is selected depends on the fast blank input signals and the programming of a number of I2C-bus register settings (see Table 2-3 and Fig. 2-25). Both fast blank inputs must be either active-low or active-high. All signals for analog RGB insertion (RIN1/2, GIN1/2, BIN1/2, FBLIN1/2, HCS) must be synchronized to the horizontal flyback, otherwise a horizontal jitter will be visible. The VDP 31xxB has no means for timing correction of the analog RGB input signals. Table 2-3: RGB Input Selection FBFOH1 = 0, FBFOH2 = 0, FBFOL1 = 0, FBFOL2 = 0 FBLIN1 0 0 1 1 FBLIN2 0 1 0 1 1 0 0 1 0 1 FBPOL 0 0 0 0 0 1 1 1 1 1 FBPRIO x x x 0 1 0 1 x x x RGB output Video RGB input 2 RGB input 1 RGB input 1 RGB input 2 RGB input 1 RGB input 2 RGB input 1 RGB input 2 Video 2.9.3. Average Beam Current Limiter The average beam current limiter (BCL) uses the sense input for the beam current measurement. The BCL uses a different filter to average the beam current during the active picture. The filter bandwidth is approx. 2 kHz. The beam current limiter has an automatic offset adjustment that is active two lines before the first cutoff measurement line. The beam current limiter function is located in the frontend. The data exchange between the front-end and the back-end is done via a single-wire serial interface. The beam current limiter allows the setting of a threshold current. If the beam current is above the threshold, the excess current is low-pass filtered and used to attenuate the RGB outputs by adjusting the white-drive multipliers for the internal (digital) RGB signals, and the analog contrast multipliers for the analog RGB inputs, respectively. The lower limit of the attenuator is programmable, thus a minimum contrast can always be set. During the tube measurement, the ABL attenuation is switched off. After the white drive measurement line it takes 3 lines to switch back to BCL limited drives and brightness. Typical characteristics of the ABL for different loop gains are shown in Fig. 2-24; for this example the tube has been assumed to have square law characteristics. beam current 1 0 0 0 1 1 drive Fig. 2-24: Beam current limiter characteristics: beam current output vs. drive BCL threshold: 1 Micronas 23 VDP 31xxB 2.9.5. Fast Blank Monitor The presence of external analog RGB sources can be detected by means of a fast blank monitor. The status of the selected fast blank input can be monitored via an I2C bus register. There is a 2 bit information, giving static and dynamic indication of a fast blank signal. The static bit is directly reading the fast blank input line, whereas the dynamic bit is reading the status of a flip-flop triggered by the negative edge of the fast blank signal. With this monitor logic it is possible to detect if there is an external RGB source active and if it is a full screen insertion or only a box. The monitor logic is connected directly to the FBLIN1 or FBLIN2 pin. Selection is done via I2C bus register. PRELIMINARY DATA SHEET 2.9.6. Half Contrast Control Insertion of transparent text pages or OSD onto the video picture is often difficult to read, especially if the video contrast is high. The VDP 31xxB allows contrast reduction of the video background by means of a half contrast input (HCS pin). This input can be supplied with a fast switching signal (similar to the fast blank input), typically defining a rectangular box in which the video picture is displayed with reduced contrast. The analog RGB inputs are still displayed with full contrast. The HCS input is multiplexed with the PORT0 input/output on the same pin, selection is done via I2C-bus register. If the HCS input is selected, then the port function of this pin is disabled and writing data into PORT0 will have no effect. If the HCS input is not selected, the I2C-bus register bits HCSFOH and HCSPOL must be used to disable the half contrast function. HCSPOL FBFOH1 FBFOL1 FBPOL FBPRIO FBLIN1 # HCS FB int Fast Blank Monitor FBLIN2 Fast Blank Selection # HCS intern # HCSEN HCSFOH Fig. 2-26: Half Contrast Switch Logic FBFOH2 FBFOL2 FBMON 2.10. IO Port Expander The VDP 31xxB provides a general purpose IO port to control and monitor up to seven external signals. The port direction is programmable for each bit individually. Via I2C bus register it is possible to write or read each port pin. Because of the relatively low I2C bus speed, only slow or static signals can be handled. The port signals are multiplexed with other signals to minimize pin count. PORT0 is multiplexed with the HCS input signal, PORT1 is multiplexed with the FSY output signal, PORT[6:2] are multiplexed with the color bus input COLOR[4:0]. The pin configuration is programmable via I2C bus register. All register bits can be read back, the default configuration after reset is input on PORT[1:0] and COLOR[4:0] enabled. Fig. 2-25: Fast Blank Selection Logic 24 Micronas PRELIMINARY DATA SHEET VDP 31xxB digital SVM in 8 8 bit DAC SVM 1.88mA 0.94mA int. brightness * white drive R analog SVM out HCS cutoff R 9 bit DAC 1.5 mA digital R in 10 10 bit DAC Video 3.75mA int. brightness * white drive G 9 bit DAC 2.2 mA blanking 750 A analog R out cutoff G 9 bit DAC 1.5 mA digital G in 10 10 bit DAC Video 3.75mA int. brightness * white drive B 9 bit DAC 2.2 mA blanking 750 A analog G out cutoff B 9 bit DAC 1.5 mA digital B in 10 10 bit DAC Video 3.75mA 9 bit DAC 2.2 mA blanking 750 A analog B out H ext. brightness * white drive R ext. brightness * white drive G ext. brightness * white drive B V serial interface white drive R white drive G 9 bit DAC 1.5 mA 9 bit DAC 1.5 mA 9 bit DAC 1.5 mA blank & measurem. timing ext. contrast * white drive R * beam current lim. ext. contrast * white drive G * beam current lim. white drive B int . brightness ext. contrast ext. brightness 9 bit U/I-DAC 3.75mA clamp & mux 9 bit U/I-DAC 3.75mA clamp & mux ext. contrast * white drive B * beam current lim. 9 bit U/I-DAC 3.75mA clamp & mux FBL prio 8 bit ADC measurm. key 1 2 analog R in 1 2 analog G in 1 2 analog B in 1 2 fast blank in Sense Input Fig. 2-27: Analog back-end Micronas measurement buffer I/O 25 VDP 31xxB 2.11. Synchronization and Deflection The synchronization and deflection processing is distributed over front-end and back-end. The video clamping, horizontal and vertical sync separation and all video related timing information are processed in the front-end. Most of the processing that runs at the horizontal frequency is programmed on the internal Fast Processor (FP). Also the values for vertical and East/ West deflection are calculated by the FP software. The information extracted by the video sync processing is multiplexed onto the hardware front sync signal (FSY) and distributed internally to the rest of the video processing system. The data for the vertical deflection, the sawtooth and the East/West correction signal is calculated in the front end. The data is transferred to the back-end by a single wire interface. The display related synchronization, i.e. generation of horizontal and vertical drive and synchronization of horizontal and vertical drive to the video timing extracted in the front-end, are implemented in hardware in the backend. 2.11.1. Deflection Processing The deflection processing generates the signals for the horizontal and vertical drive (see Fig. 2-28). This block contains two phase-locked loops: - PLL2 generates the horizontal and vertical timing, e.g. blanking, clamping and composite sync. Phase and frequency are synchronized by the front sync signal. - PLL3 adjusts the phase of the horizontal drive pulse and compensates for the delay of the horizontal output stage. Phase and frequency are synchronized by the oscillator signal of PLL2. The horizontal drive circuitry uses a digital sine wave generator to produce the exact (subclock) timing for the drive pulse. The generator runs at 1 MHz; in the output PRELIMINARY DATA SHEET stage the frequency is divided down to give drive-pulse period and width. In standby mode, the output stage is driven from an internal 1 MHz clock that is derived from the 5 MHz clock signal and a fixed drive pulse width is used. When the circuit is switched out of standby operation, the drive pulse width is programmable. The horizontal drive uses an open drain output transistor. The Main Sync (MSY) signal that is generated from PLL3 is a multiplex of all display-related data (Fig. 2-29). This signal is intended for use by other processors, e.g. a PIP processor can use this signal to adjust to a certain display position. 2.11.2. Horizontal Phase Adjustment This section describes a simple way to align PLL phases and the horizontal frame position. 1. The parameter NEWLIN in the front-end has to be adjusted. The minimum possible value is 34 (recommended for a standard 4:3 signal). 2. With HDRV, the duration of the horizontal drive pulse has to be adjusted. 3. With POFS2, the clamping pulse for the analog RGB input has to be adjusted to the correct position, e.g. the pedestal of the generator signal. 4. With POFS3, the horizontal position of the analog RGB signal (from SCART) has to be adjusted. 5. With HPOS, the digital RGB output signal (from VPC) has to be adjusted to the correct horizontal position. 6. With HBST and HBSO, the start and stop values for the horizontal blanking have to be adjusted. Note: The processing delay of the internal digital video path differs depending on the comb filter option of the VDP 31xxB. The versions with comb filter have an additional delay of 35 clock cycles. Therefore, the timing of the external analog RGB signals has to be adjusted (with POFS2 and POFS3) according to the actual hardware version of the VDP 31xxB. The hardware version can be read out via FP subaddress 0xF1. 26 Micronas PRELIMINARY DATA SHEET VDP 31xxB H flyback PLL3 MSY main sync generator skew measure- ment phase comparator & lowpass DCO sinewave DAC & generator LPF 1:64 & output stage H drive blanking, clamping, etc. Standby clock display timing front sync interface phase comparator & lowpass PLL2 line counter composite sync generator CSY FSY DCO vertical reset clock & control V flyback E/W correction VDATA vertical serial data sawtooth PWM 15 bit E/W ouput PWM 15 bit V output Fig. 2-28: Deflection processing block diagram M1 input analog video M1 M2 M2 (not in scale) timing reference for PICTURE bus - chroma multiplex sync - active picture data after xxx clocks line [0] line not not not not not [8] used used used used used V: F line [7] Parity V Parity MSY Vert. blanking 0 = off 1 = on F: Field # 0 = Field 1 1 = Field 2 line: Field line # 1...N Fig. 2-29: Main sync format Micronas 27 VDP 31xxB 2.11.3. Vertical and East/West Deflection The calculations of the vertical and East/West deflection waveforms is done by the internal Fast Processor (FP). The algorithm uses a chain of accumulators to generate the required polynomial waveforms. To produce the deflection waveforms, the accumulators are initialized at the beginning of each field. The initialization values must be computed by the TV control processor and are written to the front-end once. The waveforms are described as polynomials in x, where x varies from 0 to 1 for one field. P: a + b(x-0.5) + c(x-0.5)2 + d(x-0.5)3 + e(x-0.5)4 The initialization values for the accumulators a0..a3 for vertical deflection and a0..a4 for East/West deflection are 12-bit values. The vertical waveform can be scaled according the average beam current. This is used to compensate the effects of electric high tension changes due to beam current variations. In order to get a faster vertical retrace timing, the output impedance of the vertical D/A-converter can be reduced by 50% during the retrace. Fig. 2-30 shows several vertical and East/West deflection waveforms. The polynomial coefficients are also stated. PRELIMINARY DATA SHEET 2.11.4. Protection Circuitry - Picture tube and drive stage protection is provided through the following measures: - Vertical flyback protection input: this pin searches for a negative edge in every field, otherwise the RGB drive signals are blanked. - Drive shutoff during flyback: this feature can be selected by software. - Safety input pin: this input has two thresholds. Between zero and the lower threshold, normal functioning takes place. Between the lower and the higher threshold, the RGB signals are blanked. Above the higher threshold, the RGB signals are blanked and the horizontal drive is shut off. Both thresholds have a small hysteresis. - The main oscillator and the horizontal drive circuitry are run from a separate (standby) power supply and are already active while the TV set is powering up. Vertical: a,b,c,d 0,1,0,0 0,1,1,0 0,1,0,1 East/West: a,b,c,d,e 0,0,1,0,0 0,0,0,0,1 0,0,1,1,1 Fig. 2-30: Vertical and East/West deflection waveforms 28 Micronas PRELIMINARY DATA SHEET VDP 31xxB In the standby mode the following functions are still available (see also 2.11.1.): - 20.25 MHz crystal oscillator - 5 MHz clock output (CLK5) - horizontal drive output (HOUT) The clock source for the horizontal output generator is switched to the standby clock which is derived from the 5 MHz clock. The duty cycle of HOUT is set to 50%. Protection modes with safety and horizontal flyback pins are not available. The VDP 31xxB has clock and voltage supervision circuits to generate a stable HOUT signal during power-on and standby. The HOUT signal is disabled until a proper CLK5 signal (5 MHz clock) is detected. When released, the HOUT generator runs with the standby clock. Coupling the HOUT generator to the deflection PLL has to be done by CCU using the EHPLL bit. Fig. 2-32 shows the signals during power-on and standby. 2.12. Reset Function Reset of most VDP 31xxB functions is performed by the RESET pin. When this pin becomes active, all internal registers and counters are lost. When the RESET pin is released, the internal reset is still active for 4 s. After that time, the initialization of all required registers is performed by the internal Fast Processor. During this initialization procedure (see Fig. 2-31) it is not possible to access the VDP 31xxB via the serial interface (I2C). Access to other ICs via the serial bus is possible during that time. The 5 MHz clock divider and the 1 MHz standby clock divider are not affected by reset. The clock source for the horizontal output generator is switched to the standby clock during reset. Reset Internal Reset Initialization 4s approx. 60s VSTBY XTAL 1 s CLK5 Fig. 2-31: External Reset 2.13. Standby and Power-On In standby mode the whole signal processing of the VDP 31xxB is disabled and only some basic functions are working. The standby mode is realized by switching off the supplies for analog front-end (VSUPF), analog backend (VSUPO) and digital circuitry (VSUPD). The standby supply (VSTBY) still has its nominal voltage. To disable all the analog and digital functions, it is necessary to bring the analog and digital supplies below 0.5 V. Only this guarantees that all the normal functions are disabled and the standby current for analog and digital supply is at its minimum. When switched off, the negative slope of the supply voltage VSUPD should not be larger than approximately 0.2 V/s (see Recommended Operating Conditions). In the standby mode, all registers and counter values in the VDP 31xxB are lost, they will be re-initialized via the internal Fast Processor after analog and digital supplies are switched on again and the RESET pin is released. Clock Release HOUT standby mode VSUPD RESET Fig. 2-32: Power-On, Standby On/Off Switching the HOUT signal into standby mode can be done by the CCU via the EHPLL bit or by the internal voltage supervision. The voltage supervision activates a power-down signal when the supply for the digital circuits (VSUPD) goes below X4.5 V for more than 50ns. This power down signal is extended by 50s after VSUPD is back again. The power-down signal switches the clock source for the HOUT generation to the standby clock and sets the duty cycle to 50%. This is exactly what the EHPLL bit does. As the clocks from the deflection PLL and the standby clock are not in phase, the actual phase (High/Low) of the HOUT signal may be up to one PLL or standby clock (X1 s) longer than a regular one when the clock source is changed. 29 Micronas VDP 31xxB 3. Serial Interface 3.1. I2C-Bus Interface Communication between the VDP and the external controller is done via I2C-bus. The VDP has two I2C-bus slave interfaces (for compatibility with VPC/DDP applications) - one in the front-end and one in the backend. Both I2C-bus interfaces use I2C clock synchronization to slow down the interface if required. Both I2C-bus interfaces use one level of subaddress: the I2C-bus chip address is used to address the IC and a subaddress selects one of the internal registers. The I2C-bus chip addresses are given below: PRELIMINARY DATA SHEET 3.2. Control and Status Registers Table 3-1 gives definitions of the VDP control and status registers. The number of bits indicated for each register in the table is the number of bits implemented in hardware, i.e. a 9-bit register must always be accessed using two data bytes but the 7 MSB will be `don't care' on write operations and `0' on read operations. Write registers that can be read back are indicated in Table 3-1. Functions implemented by software in the on-chip control microprocessor (FP) are explained in Table 3-3. A hardware reset initializes all control registers to 0. The automatic chip initialization loads a selected set of registers with the default values given in Table 3-1. The register modes given in Table 3-1 are - w: - w/r: - r: - v: - h: write only register write/read data register read data from VDP register is latched with vertical sync register is latched with horizontal sync Chip Address front-end back-end A6 A5 A4 A3 A2 A1 A0 R/W 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1/0 1/0 The registers of the VDP have 8 or 16-bit data size; 16-bit registers are accessed by reading/writing two 8-bit data words. Figure 3-1 shows I2C-bus protocols for read and write operations of the interface; the read operation requires an extra start condition and repetition of the chip address with read command set. The mnemonics used in the Micronas VDP demo software are given in the last column. S 1000 111 W Ack 0111 1100 Ack 1 or 2 byte Data Ack P I2C write access subaddress 7c high byte Data low byte Data Ack Nak P S 1000 111 W Ack 0111 1100 Ack S 1000 111 R Ack I2C read access subaddress 7c SDA S SCL 1 0 P W R Ack Nak S P = = = = = = 0 1 0 1 Start Stop Fig. 3-1: I2C-bus protocols 30 Micronas PRELIMINARY DATA SHEET VDP 31xxB Table 3-1: I2C control and status registers of front-end I2C Sub address Number of bits Mode Function Default Name FP INTERFACE h'35 8 r FP status bit [0] bit [1] bit [2] bit[8:0] bit[11:9] bit[8:0] bit[11:9] bit[11:0] FPSTA write request read request busy 9-bit FP read address reserved, set to zero 9-bit FP write address reserved, set to zero FP data register, reading/writing to this register will autoincrement the FP read/ write address. Only 16 bit of data are transferred per I2C telegram. FPRD FPWR FPDAT h'36 h'37 h'38 16 16 16 w w w/r BLACK LINE DETECTOR h'12 16 w/r read only register, do not write to this register! after reading, LOWLIN and UPLIN are reset to 127 to start a new measurement bit[6:0] number of lower black lines bit[7] always 0 bit[14:8] number of upper black lines bit[15] 0/1 normal/black picture BLKLIN LOWLIN UPLIN BLKPIC PIN CIRCUITS h'1F 16 w/r INTLC & PORT pins: bit[2:0] 0..7 output strength for INTLC & PORT Pins (7 = tristate, 6 = weak ... 0 = strong) bit[3] 0 reserved (set to 0) bit[4] 0/1 pushpull/tristate for INTLC Pin bit[5] 0/1 synchronization/no synchronization with horizontal MSY for signal INTLC bit[15:6] reserved (set to 0) SYNC GENERATOR CONTROL: bit[6:0] 0 reserved (set to 0) bit[7] 0/1 positive/negative polarity for INTLC signal 0 0 0 TRPAD SNCSTR SNCDIS VASYSEL h'20 8 w/r SYNMODE 0 INTLCINV PRIORITY BUS h'24 8 w/r priority bus ID register and control bit [2:0] 0..7 priority ID, 0 highest bit [4:3] 0..3 pad driver strength, 0 (strong) to 3 (weak) bit [5] 0/1 reserved (set to 0) bit [6] 0/1 source for prio request: active video/clamp_to_1 bit [7] 0/1 disable/enable priority interface, if disabled frontend is disconnected from priority bus! PRIOMODE 0 0 0 0 0 PID PRIOSTR PIDSRC PIDE Micronas 31 VDP 31xxB PRELIMINARY DATA SHEET I2C Sub address Number of bits Mode Function Default Name SYNC GENERATOR h'21 16 w/r LINE LENGTH: bit[10:0] bit[15:11] h'29 16 w/r AVO STOP: bit[10:0] bit[11] 0/1 bit[13:12] 00 01 10 11 bit[14] 0/1 bit[15] 0/1 NEWLINE: bit[10:0] LINE LENGTH register LINE LENGTH has to be set to 1295 for correct adjustment of vertical signals. reserved (set to 0) reserved (set to 0) disable/enable test pattern generator luma output mode: Y = rampe (240 ... 17) Y = 16 Y = 90 Y = 240 reserved (set to 0) chroma output: pseudo color bar/zero NEWLINE register This register defines the readout start of the next line in respect to the value of the sync counter. Value of this register must be greater than 31 for correct operation. reserved (set to 0) 1295 LINLEN AVSTOP 0 0 0 COLBAREN LMODE 0 0 50 CMODE NEWLIN h'22 16 w/r bit [15:11] 32 Micronas PRELIMINARY DATA SHEET VDP 31xxB Table 3-2: Backend I2C-control and status registers I2C sub address Number of bits Mode Function Default Name PRIORITY BUS priority mask register, if bit[x] is set to 1 then the function is active for the respective signal priority h'75 h'71 h'7d h'79 h'4b h'47 9 9 9 9 9 9 wv wv wv wv wv wv bit [7:0] bit [7:0] bit [7:0] bit [7:0] bit [7:0] bit [2:0] bit [8] bit[x] 0/1: select contrast,brightness,matrix for main/side picture bit[x] 0/1: select main (video)/external (via CLUT) RGB bit[x] 0/1: enable/disable black level expander bit[x] 0/1: disable/enable peaking transient suppression when signal is switched bit[x] 0/1: disable/enable analog fast blank input picture frame generator priority id enable prio id for picture frame generator 0 0 0 0 0 0 PBCT PBERGB PBBLE PBPK PBFB PFGID PFGEN LUMA CHANNEL h'61 h'65 h'51 h'55 h'59 9 9 9 9 9 wv wv wv wv wv bit [5:0] bit [5:0] bit [8:0] bit [8:0] 0..63/32 0..63/32 -256..255 -256..255 main picture contrast side picture contrast main picture brightness side picture brightness tilt coefficient amount disable expansion, threshold value 32 32 0 0 8 12 200 CTM CTS BRM BRS BTLT BAM BTHR black level expander: bit [3:0] 0..15 bit [8:4] 0...31 black level expander: bit [8:0] 0..511 h'5d h'69 9 9 wv wv luma peaking filter, the gain at high frequencies and small signal amplitudes is: 1 + (k1+k2)/8 bit [3:0] 0..15 k1: peaking level undershoot bit [7:4] 0..15 k2: peaking level overshoot bit [8] 0/1 peaking value normal/inverted (peaking/softening) luma peaking filter, coring bit [4:0] 0..31 coring level bit [7:5] reserved bit [8] 0/1 peaking filter center frequency high/low luma soft limiter, slope A and B bit [3:0] slope segment A bit [7:4] slope segment B bit [7:0] bit [8] 0/1 bit [8:0] bit [8:0] luma soft limiter absolute limit (unsigned) modulation off/on luma soft limiter segment B tilt point (unsigned) luma soft limiter segment A tilt point (unsigned) 4 4 0 PKUN PKOV PKINV h'6d 9 wv 3 0 0 0 255 1 300 250 COR PFS LSLSA LSLSB LSLAL LSLM LSLTB LSLTA h'41 9 wv h'45 h'49 h'4d 9 9 9 wv wv wv Micronas 33 VDP 31xxB PRELIMINARY DATA SHEET I2C sub address Number of bits Mode Function Default Name CHROMA CHANNEL h'14 8 w/r luma/chroma matching delay bit [2:0] -3...3 variable chroma delay bit [3] 0/1 chroma polarity signed / offset binary bit [4] 0/1 CB (U) sample first / CR (V) sample first bit [7:5] reserved, set to 0 digital transient improvement bit [3:0] 0..15 coring value bit [7:4] 0..15 DTI gain bit [8] 0/1 narrow/wide bandwidth mode 0 1 0 0 1 5 1 LDB COB ENVU h'66 9 wv DTICO DTIGA DTIMO INVERSE MATRIX h'7c h'74 h'6c h'64 h'5c h'54 h'78 h'70 h'68 h'60 h'58 h'50 9 9 9 9 9 9 9 9 9 9 9 9 wv wv wv wv wv wv wv wv wv wv wv wv main picture matrix coefficient R-Y = MR1M*CB + MR2M*CR bit [8:0] -256/128 ... 255/128 bit [8:0] -256/128 ... 255/128 main picture matrix coefficient G-Y = MG1M*CB + MG2M*CR bit [8:0] -256/128 ... 255/128 bit [8:0] -256/128 ... 255/128 main picture matrix coefficient B-Y = MB1M*CB + MB2M*CR bit [8:0] -256/128 ... 255/128 bit [8:0] -256/128 ... 255/128 side picture matrix coefficient R-Y = MR1S*CB + MR2S*CR bit [8:0] -256/128 ... 255/128 bit [8:0] -256/128 ... 255/128 side picture matrix coefficient G-Y = MG1S*CB + MG2S*CR bit [8:0] -256/128 ... 255/128 bit [8:0] -256/128 ... 255/128 side picture matrix coefficient B-Y = MB1S*CB + MB2S*CR bit [8:0] -256/128 ... 255/128 bit [8:0] -256/128 ... 255/128 0 86 -22 -44 113 0 0 73 -19 -37 97 0 MR1M, MR2M MG1M, MG2M MB1M, MB2M MR1S, MR2S MG1S, MG2S MB1S, MB2S COLOR LOOK-UP TABLE color look-up table : 16 entries, 12 bit wide, The CLUT registers are initialized at power-up bit [3:0] 0..15 blue amplitude bit [7:4] 0..15 green amplitude bit [11:8] 0..15 red amplitude 000h f00h 0f0h ff0h 00fh f0fh 0ffh fffh 7ffh 700h 070h 770h 007h 707h 077h 777h 0 0 0 CLUT0 h'00- h'0f 16 wh CLUT15 PFCB PFCG PFCR h'11 16 wh picture frame color 12 bit wide, bit [3:0] 0..15 blue amplitude bit [7:4] 0..15 green amplitude bit [11:8] 0..15 red amplitude 34 Micronas PRELIMINARY DATA SHEET VDP 31xxB I2C sub address Number of bits Mode Function Default Name h'4c 9 wv digital OSD insertion contrast for R (amplitude range: 0 to 255) bit [3:0] 0..13 R amplitude = CLUTn * (DRCT + 4) 14,15 invalid picture frame insertion contrast for R (ampl. range: 0 to 255) bit [7:4] 0..13 R amplitude = PFCR * (PFRCT + 4) 14,15 invalid digital OSD insertion contrast for G (amplitude range: 0 to 255) bit [3:0] 0..13 G amplitude = CLUTn * (DGCT + 4) 14,15 invalid picture frame insertion contrast for G (ampl. range: 0 to 255) bit [7:4] 0..13 G amplitude = PFCG * (PFGCT + 4) 14,15 invalid digital OSD insertion contrast for B (amplitude range: 0 to 255) bit [3:0] 0..13 B amplitude = CLUTn * (DBCT + 4) 14,15 invalid picture frame insertion contrast for B (ampl. range: 0 to 255) bit [7:4] 0..13 B amplitude = PFCB * (PFBCT + 4) 14,15 invalid 8 8 DRCT PFRCT h'48 9 wv 8 8 DGCT PFGCT h'44 9 wv 8 8 DBCT PFBCT PICTURE FRAME GENERATOR h'4F 9 wv bit [8:0] horizontal picture frame begin code 0 = picture frame generator horizontally disabled code 1FF = full frame bit [8:0] horizontal picture frame end bit [8:0] vertical picture frame begin code 0 = picture frame generator vertically disabled bit [8:0] vertical picture frame end enable and priority - see under `PRIORITY BUS' picture frame color - see under `COLOR LOOK-UP TABLE' SCAN VELOCITY MODULATION h'62 9 wv video mode coefficients bit [5:0] gain1 bit [8:6] differentiator delay 1 (0= filter off, 1...6= delay) text mode coefficients bit [5:0] gain 2 bit [8:6] differentiator delay 2 (0= filter off, 1...6= delay) limiter bit [6:0] bit [8:5] limit value not used, set to "0" 60 4 60 4 100 0 7 0 SVG1 SVD1 SVG2 SVD2 SVLIM 0 PFGHB h'53 h'63 h'6f 9 9 9 wv wv wv 0 270 56 PFGHE PFGVB PFGVE h'5e 9 wv h'5a 9 wv h'56 9 wv delay and coring bit [3:0] adjustable delay, in 1/2 display clock steps, (value 5 : delay of SVMOUT is the same as for RGBOUT bit [7:4] coring value bit [8] not used, set to "0" SVDEL SVCOR Micronas 35 VDP 31xxB PRELIMINARY DATA SHEET I2C sub address Number of bits Mode Function Default Name DISPLAY CONTROLS h'52 h'4e h'4a 9 9 9 wv wv wv cutoff Red cutoff Green cutoff Blue 0 0 0 CR CG CB TUBE AND PICTURE MEASUREMENT h'7b h'6b h'7f h'25 9 9 9 8 wv wv wv w/r picture measurement start line bit [8:0] (TML+9)..511 first line of picture measurement picture measurement stop line bit [8:0] (PMST+1)..511 last line of picture measurement tube measurement line bit [8:0] 0..511 start line for tube measurement tube and picture measurement control bit [0] 0/1 disable/enable tube measurement bit [1] 0/1 80/40 kHz bandwidth for picture measurement bit [2] 0/1 disable/enable picture measurement (writing a '1' starts one measurement cycle) bit [3] 0/1 large/small picture measurement window, will be disabled from bit[3] in address h'32 bit [4] 0/1 measure / offset check for adc bit [7:5] reserved white drive measurement control bit [9:0] 0..1023 RGB values for white drive beam current measurement bit [10] reserved bit [11] 0/1 RGB values for white drive beam current measurement disabled/enabled measurement result registers minimum in active picture maximum in active picture white drive cutoff/leakage red cutoff/leakage green cutoff/leakage blue, read pulse starts tube measurement measurement adc status and fast blank input status measurement status register bit [0] 0/1 tube measurement active / complete bit [2:1] white drive measurement cycle 00 red 01 green 10 blue 11 reserved bit [3] 0/1 picture measurement active / complete bit [4] 0/1 fast blank input low / high (static) bit [5] 1 fast blank input negative transition since last read (bit reset at read) bit [7:6] reserved 23 308 15 0 PMST PMSO TML PMC TMEN PMBW PMEN PMWIN OFSEN h'13 16 w/r 512 0 - WDRV EWDM 8 h'18 h'19 h'1a h'1d h'1c h'1b h'1e 8 r MRMIN MRMAX MRWDR MRCR MRCG MRCB - PMS r 36 Micronas PRELIMINARY DATA SHEET VDP 31xxB I2C sub address Number of bits Mode Function Default Name TIMING h'67 h'77 h'73 9 9 9 wv wv wv vertical blanking start bit [8:0] 0..511 first line of vertical blanking vertical blanking stop bit [8:0] 0..511 last line of vertical blanking start of Black Level Expander measurement bit [8:0] 0..511 first line of measurement, stop with first line of vertical blanking bit [8:0] free running field period = (value)4) lines 305 25 30 0 VBST VBSO AVST STIMP h'5f 9 wv HORIZONTAL DEFLECTION h'7a 9 wv adjustable delay of PLL2, clamping, and blanking (relative to front sync) adjust clamping pulse for analog RGB input bit [8:0] -256..+255 " 8 s adjustable delay of flyback, main sync, csync and analog RGB (relative to PLL2) adjust horizontal drive or csync bit [8:0] -256..+255 "8 s adjustable delay of main sync (relative to flyback) adjust horizontal position for digital picture bit [8:0] 20 steps+1 s start of horizontal blanking bit [8:0] 0..511 end of horizontal blanking bit [8:0] 0..511 PLL2/3 filter coefficients, 1of5 bit code (n+ set bit number) bit [5:0] proportional coefficient PLL3, 2-n-1 bit [5:0] proportional coefficient PLL2, 2-n-1 bit [5:0] integral coefficient PLL2, 2-n-5 horizontal drive and vertical signal control register bit [5:0] 0..63 horizontal drive pulse duration in ms (internally limited to 4..61) bit [6] 0/1 disable/enable horizontal PLL2 and PLL3 bit [7] 0/1 1: disable horizontal drive pulse during flyback bit [8] 0/1 reserved, set to '0' bit [9] 0/1 enable/disable ultra black blanking bit [10] 0/1 0: all outputs blanked 1: normal mode bit [11] 0/1 enable/disable clamping for analog RGB input bit [12] 0/1 disable/enable vertical free running mode (FIELD is set to field2, no interlace) bit [13] 0/1 enable/disable vertical protection bit [14] 0/1 internal/external (under VPC control) start of vertical and E/W signal bit [15] 0/1 disable/enable phase shift of display clock -141 POFS2 h'76 9 wv 0 POFS3 h'7e 9 wv 120 HPOS h'5b h'57 9 9 w/r w/r 1 48 2 1 2 32 0 0 0 1 0 0 0 0 1 HBST HBSO PKP3 PKP2 PKI2 HDRV EHPLL EFLB DUBL EBL DCRGB SELFT DVPR XDEFL DISKA h'6a h'6e h'72 h'15 9 9 9 16 wv wv wv w/r Micronas 37 VDP 31xxB PRELIMINARY DATA SHEET I2C sub address Number of bits Mode Function Default Name OUTPUT PINS h'10 8 w/r output pin configuration bit [2:0] pin driver strength, MSY and CSY 7 = tristate 6 = minimum strength 0 = maximum strength bit [4:3] reserved (set to 0) bit [5] 0/1 disable/enable internal resistor for vertical and East/West drive output bit [7:6] function of CSY pin : 00 composite sync signal output 01 25 Hz output (field1/field2 signal) 10 no interlace (field 2), output = 0 11 1 MHz horizontal drive clock 0 PSTSY VEWXR CSYM MISCELLANEOUS h'32 8 w/r fast blank interface mode bit [0] 0 internal fast blank 1 from FBLIN1 pin 1 force internal fast blank 1 signal to high bit [1] 0/1 internal fast blank active high/low bit [2] 0/1 disable/enable clamping reference for RGB outputs bit [3] 1 full line MADC measurement window, disables bit [3] in address h'25 bit [4] 0/1 horizontal flyback input active high/low bit [6:5] reserved (set to 0) bit [7] 0 internal fast blank 1 from FBLIN1 pin 1 force internal fast blank 1 signal to low fast blank interface mode 2 bit [0] 0 internal fast blank 2 from FBLIN2 pin 1 force internal fast blank 2 signal to high bit [1] 0 internal fast blank 2 from FBLIN2 pin 1 force internal fast blank 2 signal to low bit [2] fast blank input priority 0 FBLIN1 > FBLIN2 1 FBLIN1 < FBLIN2 bit [3] fast blank monitor input select 0 monitor connected to FBLIN1 pin 1 monitor connected to FBLIN2 pin bit [4] half contrast switch enable 0 PORT0 enable / HCS disable 1 PORT0 disable / HCS enable bit [5] 0 half contrast from HCS pin 1 force half contrast signal to high bit [6] 0/1 half contrast active high/low at HCS pin bit [7] reserved (set to 0) IO Port bit [6:0] bit [7] 0 1 bit [14:8] 0 1 bit [15] 0 1 data to/from PORT[6:0] front sync output at PORT1 PORT1 input/output enable FSY output enable port direction switch PORT[bit-8] to input switch PORT[bit-8] to output port enable COLOR[4:0] enable / PORT[6:2] disable COLOR[4:0] disable / PORT[6:2] enable 0 FBMOD FBFOH1 FBPOL CLMPR FLMW FLPOL FBFOL1 0 FBMOD2 FBFOH2 FBFOL2 FBPRIO FBMON HCSEN HCSFOH HCSPOL 0 IOPORT IODATA FSYOEN IODIR IOEN h'31 8 w/r h'34 16 w/r 38 Micronas PRELIMINARY DATA SHEET VDP 31xxB Table 3-3: Control Registers of the Fast Processor for control of front-end functions - default values are initialized at reset FP Subaddress Function Default Name Standard Selection h'20 Standard select: bit[2:0] standard 0 PAL B,G,H,I (50 Hz) 4.433618 1 NTSC M (60 Hz) 3.579545 2 SECAM (50 Hz) 4.286 3 NTSC44 (60 Hz) 4.433618 4 PAL M (60 Hz) 3.575611 5 PAL N (50 Hz) 3.582056 6 PAL 60 (60 Hz) 4.433618 7 NTSC COMB (60 Hz) 3.579545 bit[3] 0/1 standard modifier PAL modified to simple PAL NTSC modified to compensated NTSC SECAM modified to monochrome 625 NTSCC modified to monochrome 525 bit[4] reserved (set to 0) bit[5] 0/1 2-H comb filter off/on bit[6] 0/1 S-VHS mode off/on Option bits allow to suppress parts of the initialization, this can be used for color standard search: bit[7] bit[8] bit[9] bit[10] bit[11] no hpll setup no vertical setup no acc setup 2-H comb filter set-up only status bit, normally write 0. After the FP has switched to a new standard, this bit is set to 1 to indicate operation complete. Standard is automatically initialized when the insel register is written. 0 sfif 0 sdt pal ntsc secam ntsc44 palm paln pal60 ntscc sdtmod comb svhs sdtopt h'22 picture start position, this register sets the start point of active video, this can be used e.g. for panning. The setting is updated when 'sdt' register is updated. luma/chroma delay adjust. The setting is updated when 'sdt' register is updated. bit[5:0] reserved, set to zero bit[11:6] luma delay in clocks, allowed range is +1 ... -7 h'23 0 ldly Micronas 39 VDP 31xxB PRELIMINARY DATA SHEET FP Subaddress Function Default Name Standard Selection h'21 Input select: bit[1:0] 00 01 10 11 bit[2] 0/1 bit[4:3] 00 01 10 11 bit[6:5] 00 01 10 11 0/1 0/1 00 01 10 11 bit[11] writing to this register will also initialize the standard luma selector VIN3 VIN2 VIN1 VIN4 chroma selector VIN1/CIN IF compensation off 6 dB/Okt 12 dB/Okt 10 dB/MHz only for SECAM chroma bandwidth selector narrow normal broad wide adaptive/fixed SECAM notch filter enable luma lowpass filter hpll speed no change terrestrial vcr mixed status bit, write 0, this bit is set to 1 to indicate operation complete. Comb Filter h'27 comb filter control register bit[0] 0 comb coefficients are calculated for luma/chroma 1 comb coefficients for luma are used for luma and chroma bit[1] 0 luma comb strength depends on signal amplitude 1 luma comb strength is independent of amplitude bit[2] 0 reduced comb booster 1 max comb booster bit[4:3] 0..3 comb strength for chroma signal bit[6:5] 0..3 comb strength for luma signal bit[11:7] 0..31 overall limitation of the calculated comb coefficients 0 no limitation 31 max limitation (1/2) Color Processing h'39 h'3a h'dc amplitude killer level (0:killer disabled) amplitude killer hysteresis NTSC tint angle, 512 = /4 25 5 0 kilvl kilhy tint 0 cmb_uc cc 00 insel vis 1 00 cis ifc 01 cbw bit[7] bit[8] bit[10:9] fntch lowp hpllmd 0 1 3 2 0 daa kb kc ky clim 40 Micronas PRELIMINARY DATA SHEET VDP 31xxB FP Subaddress Function Default Name DVCO h'f8 h'f9 crystal oscillator center frequency adjust, -2048 ... 2047 crystal oscillator center frequency adjustment value for line lock mode, true adjust value is DVCO - ADJUST. For factory crystal alignment, using standard video signal: set DVCO = 0, set lock mode, read crystal offset from ADJUST register and use negative value for initial center frequency adjustment via DVCO. crystal oscillator line-locked mode, lock command/status write: 100 enable lock 0 disable lock read: 0 unlocked >2047 locked FP Status Register h'12 general purpose control bits bit[2:0] reserved, do not change bit[3] vertical standard force bit[8:4] reserved, do not change bit[9] disable flywheel interlace bit[11:10] reserved, do not change to enable vertical free run mode set vfrc to 1 and dflw to 0 h'13 standard recognition status bit[0] 1 vertical lock bit[1] 1 horizontally locked bit[2] 1 no signal detected bit[3] 1 color amplitude killer active bit[4] 1 disable amplitude killer bit[5] 1 color ident killer active bit[6] 1 disable ident killer bit[7] 1 interlace detected bit[8] 1 no vertical sync detection bit[9] 1 spurious vertical sync detection bit[11:10] reserved number of lines per field, P/S: 312, N: 262 vertical field counter, incremented per field measured sync amplitude value, nominal: 768 (PAL), 732 (NTSC) measured burst amplitude firmware version number bit[7:0] internal revision number bit[11:8] firmware release hardware version number bit[7:0] internal hardware revision number bit[11:8] hardware id 0000 = VDP 3120B 1000 = VDP 3116B 0100 = VDP 3112B 1100 = VDP 3108B 1110 = VDP 3104B read only read only read only - asr -720 read only dvco adjust h'f7 0 xlck 0 1 vfrc dflw h'cb h'15 h'74 h'31 h'f0 read only nlpf vcnt sampl bampl sw_version h'f1 read only hw_version Micronas 41 VDP 31xxB PRELIMINARY DATA SHEET FP Subaddress Function Default Name Scaler Control Register h'40 scaler mode register bit[1:0] scaler mode 0 linear scaling mode 1 nonlinear scaling mode, 'panorama' 2 nonlinear scaling mode, 'waterglass' 3 reserved bit[10:2] reserved, set to 0 bit[11] scaler update 0 start scaler update command, when the registers are updated the bit is set to 1 luma offset register bit[6:0] luma offset 0..127 ITU-R output format: 57 CVBS output format: 4 this register is updated when the scaler mode register is written active video length for 1-h FIFO bit[11:0] length in pixels this register is updated when the scaler mode register is written scaler1 coefficient, this scaler is compressing the signal. For compression by a factor c the value c*1024 is required. bit[11:0] allowed values from 1024..4095 this register is updated when the scaler mode register is written scaler2 coefficient, this scaler is expanding the signal. For expansion by a factor c the value 1/c*1024 is required. bit[11:0] allowed values from 256..1024 this register is updated when the scaler mode register is written scaler1/2 nonlinear scaling coefficient this register is updated when the scaler mode register is written scaler1 window controls, see table 5 12-bit registers for control of the nonlinear scaling this register is updated when the scaler mode register is written scaler2 window controls see table 5 12-bit registers for control of the nonlinear scaling this register is updated when the scaler mode register is written 0 scmode pano h'41 57 yoffs h'42 1080 fflim h'43 scinc1 1024 scinc2 1024 0 0 scinc scw1_0 - 4 h'44 h'45 h'47 - h'4b h'4c - h'50 0 scw2_0 - 4 42 Micronas PRELIMINARY DATA SHEET VDP 31xxB 3.2.1. Scaler Adjustment In case of linear scaling, most of the scaler registers need not be set. Only the scaler mode, active video length, and the fixed scaler increments (scinc1/scinc2) must be written. The adjustment of the scaler for nonlinear scaling modes should use the parameters given in Table 3-4. Table 3-4: Set-up values for nonlinear scaler modes Register Scaler Modes `waterglass' border 35% `panorama' border 30% center compression 3/4 scinc1 scinc2 scinc fflim scw1 - 0 scw1 - 1 scw1 - 2 scw1 - 3 scw1 - 4 scw2 - 0 scw2 - 1 scw2 - 2 scw2 - 3 scw2 - 4 1643 1024 90 945 110 156 317 363 473 110 156 384 430 540 5/6 1427 1024 56 985 115 166 327 378 493 115 166 374 425 540 4/3 1024 376 85 921 83 147 314 378 461 122 186 354 418 540 6/5 1024 611 56 983 94 153 339 398 492 118 177 363 422 540 Micronas 43 VDP 31xxB Table 3-5: Control Registers of the Fast Processor for control of back-end functions - default values are initialized at reset FP Subaddress Function PRELIMINARY DATA SHEET Default Name FP Display Control Register h'130 h'131 h'132 h'139 h'13c White Drive Red (0...1023) 700 700 700 256 256 WDR 1) WDG 1) WDB 1) IBR IBRM White Drive Green (0...1023) White Drive Blue (0...1023) Internal Brightness, Picture (0...511), the center value is 256, the range allows for both increase and reduction of brightness. Internal Brightness, Measurement (0...511), the center value is 256, the brightness for measurement can be set to measure at higher cutoff current. The measurement brightness is independent of the drive values. Analog Brightness for external RGB (0...511), the center value is 256, the range allows for both increase and reduction of brightness. Analog Contrast for external RGB (0...511) h'13a h'13b 256 350 ABR ACT 1) The white drive values will become active only after writing the blue value WDB, latching of new values is indicated by setting the MSB of WDB. FP Display Control Register, BCL h'144 h'142 h'143 h'145 h'105 BCL threshold current, 0...2047 (max ADC output ~1152) BCL time constant 0...15 13 ... 1700 msec BCL loop gain. 0..15 BCL minimum contrast 0...1023 Test register for BCL/EHT comp. function, register value: 0 normal operation 1 stop ADC offset compensation x>1 use x in place of input from Measurement ADC FP Display Control Register, Deflection h'103 h'102 interlace offset, -2048..2047 This value is added to the SAWTOOTH output during one field. discharge sample count for deflection retrace, SAWTOOTH DAC output impedance is reduced for DSCC lines after vertical retrace. vertical discharge value, SAWTOOTH output value during discharge operation, typically same as A0 init value for sawtooth. EHT (electronic high tension) compensation coefficient, 0...511 EHT time constant. 0..15 --> 3.2..410 msec 0 7 INTLC DSCC 1000 15 0 307 0 BCLTHR BCLTM BCLG BCLMIN BCLTST h'11f -1365 DSCV h'10b h'10a 0 15 EHT EHTTM 44 Micronas PRELIMINARY DATA SHEET VDP 31xxB Control Registers, continued FP Subaddress Function Default Name FP Display Control Register, Vertical Sawtooth h'110 h'11b h'11c h'11d h'11e DC offset of SAWTOOTH output This offset is independent of EHT compensation. accu0 init value accu1 init value accu2 init value accu3 init value FP Display Control Register, East-West Parabola h'12b h'12c h'12d h'12e h'12f accu0 init value accu1 init value accu2 init value accu3 init value accu4 init value -1121 219 479 -1416 1052 A0 A1 A2 A3 A4 0 -1365 900 0 0 OFS A0 A1 A2 A3 Micronas 45 VDP 31xxB 3.2.2. Calculation of Vertical and East-West Deflection Coefficients In Table 3-6 the formula for the calculation of the deflection initialization parameters from the polynomial coefficients a,b,c,d,e is given for the vertical and East-West deflection. Let the polynomial be P : a ) b(x * 0.5) ) c(x * 0.5) 2 ) d(x * 0.5) 3 ) e(x * 0.5) 4 PRELIMINARY DATA SHEET The initialization values for the accumulators a0..a3 for vertical deflection and a0..a4 for East-West deflection are 12-bit values. The coefficients that should be used to calculate the initialization values for different field frequencies are given below, the values must be scaled by 128, i.e. the value for a0 of the 50 Hz vertical deflection is a0 + (a * 128 * b * 1365.3 ) c * 682.7 * d * 682.7) 128 Table 3-6: Tables for the Calculation of Initialization values for Vertical Sawtooth and East-West Parabola Vertical Deflection 50 Hz a a0 a1 a2 a3 Vertical Deflection 60 Hz a a0 a1 a2 a3 128 b -1365.3 1083.5 c +682.7 -1090.2 429.9 d -682.7 +1645.5 -1305.8 1023.5 a0 a1 a2 a3 a4 a 128 128 b -1365.3 899.6 c +682.7 -904.3 296.4 d -682.7 +1363.4 898.4 585.9 a0 a1 a2 a3 a4 East-West Deflection 60 Hz b -341.3 134.6 c 1365.3 -1083.5 849.3 d -85.3 102.2 -161.2 125.6 e 341.3 -548.4 1305.5 -2046.6 1584.8 a 128 East-West Deflection 50 Hz b -341.3 111.9 c 1365.3 -899.6 586.8 d -85.3 84.8 -111.1 72.1 e 341.3 -454.5 898.3 -1171.7 756.5 46 Micronas PRELIMINARY DATA SHEET VDP 31xxB 4. Specifications 4.1. Outline Dimensions SPGS0016-4/3E 64 2.5 33 1 32 3.8 0.1 3 57.7 0.1 (1) 19.3 0.1 18 0.1 4.8 0.4 0.3 3.2 0.4 1.9 0.27 0.06 1.778 0.05 0.457 0.3 1 0.1 31 x 1.778 = 55.118 0.1 20.1 0.5 1.29 Fig. 4-1: 64-Pin Plastic Shrink Dual-Inline Package (PSDIP64) Weight approximately 9.0 g Dimensions in mm 4.2. Pin Connections and Short Descriptions NC = not connected; leave vacant LV = if not used, leave vacant X = obligatory; connect as described in circuit diagram Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 Pin Name TEST RESQ SCL SDA DSGND PORT0 HCS PORT1 FSY CSY MSY INTLC VPROT SAFETY HFLB IN/OUT IN/OUT OUT OUT OUT IN IN IN Type IN IN IN/OUT IN/OUT Connection (if not used) Short Description Test Pin, reserved for Test Reset Input, Active Low I2C Bus Clock I2C Bus Data Digital Shield GNDD IO Port Expander 0 / Half Contrast Switch IO Port Expander 1 / Front Sync Output Composite Sync Output Main Sync Output Interlace Control Output Vertical Protection Input Safety Input Horizontal Flyback Input GNDDF X X X X LV LV LV LV LV GNDO GNDO HOUT Micronas 47 VDP 31xxB PRELIMINARY DATA SHEET Pin No. 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Pin Name GNDDF VSUPD GNDDO PR0 PR1 PR2 COLOR4 PORT2 COLOR3 PORT3 COLOR2 PORT4 COLOR1 PORT5 COLOR0 PORT6 DSGND RSW2 RSW1 SENSE GNDM GNDV VERT EW XREF SVMOUT GNDO VSUPO ROUT GOUT BOUT VRD RIN GIN Type Connection (if not used) Short Description Ground, Digital Circuitry Front-end Supply Voltage, Digital Circuitry Ground, Digital Circuitry Back-end Picture Bus Priority Control (LSB) Picture Bus Priority Control Picture Bus Priority Control (MSB) Picture Bus Color Address 4 / IO Port Expander 2 Picture Bus Color Address 3 / IO Port Expander 3 Picture Bus Color Address 2 / IO Port Expander 4 Picture Bus Color Address 1 / IO Port Expander 5 Picture Bus Color Address 0 / IO Port Expander 6 Digital Shield GNDD Range Switch2 for Measurement ADC Range Switch1 for Measurement ADC Sense ADC Input Ground, MADC Input Ground, Vertical Outputs Vertical Sawtooth Output Vertical Parabola Output Reference Input for RGB DACs Scan Velocity Modulation Output Ground, Analog Back-end Supply Voltage, Analog Back-end Analog Red Output Analog Green Output Analog Blue Output DAC Reference Analog Red Input Analog Green Input X X X IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT LV LV LV GNDDF GNDDF GNDDF GNDDF GNDDF X OUT OUT IN GNDO GNDO GNDO X OUT OUT OUT IN OUT LV LV LV X VSUPO X X OUT OUT OUT IN IN IN VSUPO VSUPO VSUPO X GNDO GNDO 48 Micronas PRELIMINARY DATA SHEET VDP 31xxB Pin No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin Name BIN FBLIN RIN2 GIN2 BIN2 FBLIN2 CLK20 HOUT XTAL1 XTAL2 VSTBY CLK5 GNDF ISGND VRT VSUPF VOUT CIN VIN1 VIN2 VIN3 VIN4 Type IN IN IN IN IN IN OUT OUT IN OUT Connection (if not used) Short Description Analog Blue Input Fast Blank Input Analog Red Input 2 Analog Green Input 2 Analog Blue Input 2 Fast Blank Input 2 20 MHz System Clock Output Horizontal Drive Output Analog Crystal Input Analog Crystal Output Standby Supply Voltage 5 MHz Clock Output Ground, Analog Front-end Signal Ground for Analog Input Reference Voltage Top, Video ADC Supply Voltage, Analog Front-end Analog Video Output Analog Chroma Input Analog Video 1 Input Analog Video 2 Input Analog Video 3 Input Analog Video 4 Input GNDO GNDO GNDO GNDO GNDO GNDO LV X X X X OUT LV X IN IN GNDF X X OUT IN IN IN IN IN LV VRT VRT VRT VRT VRT 4.3. Pin Descriptions Pin 1 - Test Input, TEST (Fig. 4-3) This pin enables factory test modes. For normal operation it must be connected to ground. Pin 2 - Reset Input, RESQ (Fig. 4-3) A low level on this pin resets the VDP 31xxB. Pin 3 - I2C Bus Clock, SCL (Fig. 4-12) This pin connects to the I2C bus clock line. Micronas Pin 4 - I2C Bus Data, SDA (Fig. 4-12) This pin connects to the I2C bus data line. Pin 5 - Ground (Digital Shield), DSGND Pin 6, 7, 20-24 - IO Port Expander, PORT[6:0] (Fig. 4-13) These pins provide an I2C programmable I/O port, which can be used to read and write slow external signals. 49 VDP 31xxB Pin 6 - Half Contrast Switch Input, HCS (Fig. 4-16) Via this input pin the output level of the analog RGB output pins can be reduced by 3dB. Pin 7 - Front Sync Output, FSY (Fig. 4-13) This pin supplies the front sync information Pin 8 - Composite Sync Output, CSY (Fig. 4-13) This output supplies a standard composite sync signal that is compatible to the analog RGB output signals. Pin 9 - Main Sync Output, MSY (Fig. 4-13) This pin supplies the main sync information. Pin 10 - Interlace Output, INTLC (Fig. 4-13) This pin supplies the interlace information, 0 indicates first field, 1 indicates second field. Pin 11 - Vertical Protection Input, VPROT (Fig. 4-14) The vertical protection circuitry prevents the picture tube from burn-in in the event of a malfunction of the vertical deflection stage. During vertical blanking, a signal level of 2.5V is sensed. If a negative edge cannot be detected, the RGB output signals are blanked. Pin 12 - Safety Input, SAFETY (Fig. 4-14) This is a three-level input. Low level means normal function. At the medium level RGB signals are blanked and at high level RGB signals are blanked and horizontal drive is shut off. Pin 13 - Horizontal Flyback Input, HFLB (Fig. 4-14) Via this pin the horizontal flyback pulse is supplied to the VDP 31xxB. Pin 14 - Ground (Digital Circuitry Front-end), GNDDF Pin 15 - Supply Voltage (Digital Circuitry), VSUPD Pin 16 - Ground (Digital Circuitry Back-end), GNDDO Pin 17, 18, 19 - Picture Bus Priority, PR[2:0] (Fig. 4-5) The Picture Bus Priority lines carry the digital priority selection signals. The priority interface allows digital switching of up to 8 sources to the backend processor. Switching for different sources is prioritized and can be done from pixel to pixel. Pin 20...24 - Picture Bus Color Address, COLOR[4:0] (Fig. 4-16) The Picture Bus COLOR lines carry the digital RGB color data. They are used as address for the color lookup table. Pin 25 - Ground (Digital Shield), DSGND. 50 PRELIMINARY DATA SHEET Pin 26, 27 - Range Switch for Measurement ADC, RSW1, RSW2 (Fig. 4-19) These pins are open drain pull-down outputs. RSW1 is switched off during cutoff and whitedrive measurement. RSW2 is switched off during cutoff measurement only. Pin 28 - Measurement ADC Input, SENSE (Fig. 4-15) This is the input of the analog digital converter for the picture and tube measurement. Pin 29 - Ground (Measurement ADC Reference Input), GNDM This is the ground reference for the measurement A/D converter. Pin 30 - Ground (Vertical Sawtooth Output), GNDV (Fig. 4-20) This is the ground reference for the vertical outputs. Pin 31 - Vertical Sawtooth Output, VERT (Fig. 4-20) This pin supplies the drive signal for the vertical output stage. The drive signal is generated with 15-bit precision by the Fast Processor in the front-end. The analog voltage is generated by a 4-bit current-DAC with external resistor and uses digital noise shaping. Pin 32 - East-West Parabola Output, EW (Fig. 4-20) This pin supplies the parabola signal for the East-West correction. The drive signal is generated with 15 bit precision by the Fast Processor in the front-end. The analog voltage is generated by a 4-bit current-DAC with external resistor and uses digital noise shaping. Pin 33 - DAC Current Reference, XREF (Fig. 4-21) External reference resistor for DAC output currents, typical 10 k to adjust the output current of the D/A converters (see recommended operating conditions). This resistor has to be connected to analog ground as closely as possible to the pin. Pin 34 - Scan Velocity Modulation Output, SVMOUT (Fig. 4-17) This output delivers the analog SVM signal. The D/A converter is a current sink like the RGB D/A converters. At zero signal the output current is 50% of the maximum output current. Pin 35 - Ground (Analog Back-end), GNDO Pin 36 - Supply Voltage (Analog Back-end), VSUPO Pin 37, 38, 39 - Analog RGB Outputs, ROUT, GOUT, BOUT (Fig. 4-17) This are the analog Red/Green/Blue outputs of the backend. The outputs sink a current of max. 8mA. Pin 40 - DAC Reference Decoupling, VRD (Fig. 4-21) Via this pin the DAC reference voltage is decoupled by an external capacitance. The DAC output currents depend on this voltage, therefore a pull-down transistor can be used to shut off all beam currents. A decoupling capacitor of 3.3F//100nF is required. Micronas PRELIMINARY DATA SHEET VDP 31xxB Pin 59 - Analog Video Output, VOUT (Fig. 4-6) The analog video signal that is selected for the main (luma, cvbs) adc is output at this pin. An emitter follower is required at this pin. Pin 60 - Analog Chroma Input, CIN (Fig. 4-9) This pin is connected to the S-VHS chroma signal. A resistive divider is used to bias the input signal to the middle of the converter input range. CIN can only be connected to the chroma (Video 2) A/D converter. The signal must be AC-coupled. Pin 61...64 - Analog Video Input 1-4, VIN1-4 (Fig. 4-11) These are the analog video inputs. A CVBS or S-VHS luma signal is converted using the luma (Video 1) AD converter. The input signal must be AC-coupled. Pin 41, 42, 43, 45, 46, 47 - Analog RGB Inputs, RIN1/2, GIN1/2, BIN1/2 (Fig. 4-15) These pins are used to insert an external analog RGB signal, e.g. from a SCART connector which can by switched to the analog RGB outputs with the fast blank signal. The analog backend provides separate brightness and contrast settings for the external analog RGB signals. Pin 44, 48 - Fast Blank Inputs, FBLIN1/2 (Fig. 4-15) These pins are used to switch the RGB outputs to the external analog RGB inputs. Pin 49 - Main Clock Output, CLK20 (Fig. 4-4) This is the 20.25MHz main system clock, that is used by all circuits in a high-end VDP system. All external timing is derived from this clock. Pin 50 - Horizontal Drive Output, HOUT (Fig. 4-18) This open drain output supplies the the drive pulse for the horizontal output stage. The polarity and gating with the flyback pulse are selectable by software. Pin 51, 52 - Crystal Input and Output, XTAL1, XTAL2 (Fig. 4-7) These pins are connected to an 20.25 MHz crystal oscillator is digitally tuned by integrated shunt capacitances. The Clk20 and Clk5 clock signals are derived from this oscillator. An external clock can be fed into XTAL1. In this case clock frequency adjustment must be switched off. Pin 53 - Standby Supply Voltage, VSTBY In standby mode, only the clock oscillator and the horizontal drive circuitry are active. Pin 54 - CCU 5 MHz Clock Output, CLK5 (Fig. 4-10) This pin provides a clock frequency for the TV microcontroller, e.g. a CCU3000 controller. Pin 55 - Ground (Analog Front-end), GNDF Pin 56 - Ground (Analog Signal Input), ISGND (Fig. 4-8) This is the high quality ground reference for the video input signals. Pin 57 - Reference Voltage Top, VRT (Fig. 4-8) Via this pin, the reference voltage for the A/D converters is decoupled. The pin is connected with 10 mF/47 nF to the Signal Ground Pin. Pin 58 - Supply Voltage (Analog Front-end), VSUPF 4.4. Pin Configuration TEST RESQ SCL SDA DSGND PORT0/HCS PORT1/FSY CSY MSY INTLC VPROT SAFETY HFLB GNDDF VSUPD GNDDO PR0 PR1 PR2 COLOR4/PORT2 COLOR3/PORT3 COLOR2/PORT4 COLOR1/PORT5 COLOR0/PORT6 DSGND RSW2 RSW1 SENSE GNDM GNDV VERT EW 1 2 3 4 5 6 7 8 9 10 11 12 13 64 63 62 61 60 59 58 57 56 55 54 53 52 VIN4 VIN3 VIN2 VIN1 CIN VOUT VSUPF VRT ISGND GNDF CLK5 VSTBY XTAL2 XTAL1 HOUT CLK20 FBLIN2 BIN2 GIN2 RIN2 FBLIN BIN GIN RIN VRD BOUT GOUT ROUT VSUPO GNDO SVMOUT XREF VDP 31xxB 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Fig. 4-2: 64-pin PSDIP package Micronas 51 VDP 31xxB 4.5. Pin Circuits VSUPD - + PRELIMINARY DATA SHEET VSUPF P VRT Vref GNDD Fig. 4-3: Input pins RESQ, TEST Fig. 4-8: Pins VRT , ISGND ISGND VSUPD P P VSUPF To ADC N Fig. 4-4: Output pin CLK20 N GNDD GNDF Fig. 4-9: Chroma input CIN VSUPD P P N N N GNDD Fig. 4-5: Input/Output pins PR[2:0] VSTBY GNDF Fig. 4-10: Output pin CLK5 Vin's - + VSUPF P VOUT VSUPF To ADC VREF Fig. 4-6: Output pin VOUT N GNDF GNDF Fig. 4-11: Input pins VIN1-VIN4 P P 0.5M VSTBY N N f ECLK GNDD GNDF Fig. 4-12: Pins SDA, SCL Fig. 4-7: Input/Output pins XTAL1, XTAL2 52 Micronas PRELIMINARY DATA SHEET VDP 31xxB VSUPD P N N GNDD Fig. 4-13: Output pins FSY, MSY, CSY, INTLC, PORT[6:0] BIAS N VSUPO GNDO Fig. 4-17: Analog output pins ROUT, GOUT, BOUT, SVMOUT VSTDBY VSUPD N GNDD P N P N BIAS Fig. 4-18: Output pin HOUT GNDD Fig. 4-14: Input pins SAFETY, VPROT, HFLB VSUPO N VSUPO GNDM Fig. 4-19: Output pins RSW1, RSW2 P N P N GNDO Fig. 4-15: Input pins FBLIN1/2, RIN1/2, BIN1/2, GIN1/2, SENSE P P BIAS VSUPO GNDV Fig. 4-20: Output pins VERT, EW VSUPD P VSUPO VRD N GNDD Fig. 4-16: Input pins PORT[6:0] COLOR[4:0], HCS, int. ref. voltage + - ref. current XREF GNDO Fig. 4-21: Input pins XREF, VRD Micronas 53 VDP 31xxB 4.6. Electrical Characteristics 4.6.1. Absolute Maximum Ratings Symbol TA TS VSUP VI VO Parameter Ambient Operating Temperature Storage Temperature Supply Voltage, all Supply Inputs Input Voltage, all Inputs Output Voltage, all Outputs Pin No. - - Min. 0 -40 -0.3 -0.3 -0.3 PRELIMINARY DATA SHEET Max. 65 125 6 VSUP+0.3 VSUP+0.3 Unit C C V V V Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions/Characteristics" of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 4.6.2. Recommended Operating Conditions Symbol TA VSUP fXTAL Rxref NSVDD Parameter Ambient Operating Temperature Supply Voltages, all Supply Pins Clock Frequency RGB - DAC Current defining Resistor Negative Slope of VDD (power down) XTAL1/2 XREF VSUPD Pin Name - Min. 0 4.75 - 9.5 Typ. - 5.0 20.25 10 Max. 65 5.25 - 10.5 0.2 Unit C V MHz kW V/s 4.6.3. Recommended Crystal Characteristics Symbol TA fP DfP/fP DfP/fP RR C0 C1 Parameter Operating Ambient Temperature Parallel Resonance Frequency with Load Capacitance CL = 13 pF Accuracy of Adjustment Frequency Temperature Drift Series Resistance Shunt Capacitance Motional Capacitance Min. 0 - - - - 3 20 Typ. - 20.250000 - - - - - Max. 65 - $20 $30 25 7 30 Unit C MHz ppm ppm W pF fF 54 Micronas PRELIMINARY DATA SHEET VDP 31xxB Recommended Crystal Characteristics, continued Symbol Parameter Min. Typ. Max. Unit Load Capacitance Recommendation CLext External Load Capacitance 1) from pins to Ground (pin names: Xtal1 Xtal2) - 3.3 - pF DCO Characteristics 2) CICLoadmin CICLoadrng 1) Effective Load Capacitance @ min. DCO-Position, Code 0, Effective Load Capacitance Range, DCO Codes from 0..255 3.6 11.7 4.3 12.7 5 13.7 pF pF Remarks on defining the External Load Capacitance: External capacitors at each crystal pin to ground are required. They are necessary to tune the effective load capacitance of the PCBs to the required load capacitance CL of the crystal. The higher the capacitors, the lower the clock frequency results. The nominal free running frequency should match fp MHz. Due to different layouts of customer PCBs the matching capacitor size should be determined in the application. The suggested value is a figure based on experience with various PCB layouts. 720 Tuning condition: Code DVCO Register = -720 2) Remarks on Pulling Range of DCO: The pulling range of the DCO is a function of the used crystal and effective load capacitance of the IC (CICLoad +CLoadBoard). The resulting frequency fL with an effective load capacitance of CLeff = CICLoad + CLoadBoard is 1 + 0.5 * [ C1 / (C0 + CLeff ) ] fL = fP * ----------------------- 1 + 0.5 * [ C1 / (C0 + CL ) ] 4.6.4. Characteristics at TA = 0 to 65 C, VSUPD/F/O = 4.75 to 5.25 V, f = 20.25 MHz for min./max. values at TC = 60 C, VSUPD/F/O = 5 V, f = 20.25 MHz for typical values Symbol IVSUPF IVSUPD IVSUPO IVSTDBY PTOT IL Parameter Current Consumption Current Consumption Current Consumption Current Consumption Total Power Dissipation Input / Output Leakage Current All I/O Pins Pin Name VSUPF VSUPD VSUPO VSTDBY Min. - - - - - -1 Typ. 38 123 64 3.3 1145 - Max. - - - - 1200 1 Unit mA mA mA mA W mA Micronas 55 VDP 31xxB 4.6.4.1. 5 MHz Clock Output Symbol VOL VOH tOT Parameter Output Low Voltage Output High Voltage Output Transition Time Pin Name CLK5 Min. - 4.0 - Typ. - - 50 Max. 0.4 VSTDBY - PRELIMINARY DATA SHEET Unit V V ns Test Conditions IOL = 0.4 mA -IOL = 0.9 mA CLOAD = 30 pF 4.6.4.2. 20 MHz Clock Input/Output, External Clock Input (XTAL1) (see Fig. 4-22) Symbol VDCAV VPP tOT VIT fF VFMIDC VFMIAC tFMIH tFMIL tFMIHL tFMILH Parameter DC Average Pin Name CLK20 Min. VSUP/2 - 0.3 1.3 - 2.1 XTAL 1 10 1.0 0.8 Typ. VSUP/2 1.6 - 2.5 20.25 - - Max. VSUP/2 + 0.3 - 18 2.9 24 3.5 2.5 Unit V Test Conditions CLOAD = 30 pF CLOAD = 30 pF CLOAD = 30 pF only for test purposes VOUT Peak to Peak Output Transition Time Input Trigger Level FMain Clock Frequency FMain Clock Input DC Voltage FM Clock Input AC Voltage (p-p) FM Clock Input High/Low Ratio FM Clock Input High to Low Transition Time FM Clock Input Low to High Transition Time V ns V MHz V V 0.9 1.0 1.1 - - 0.15 fFM 0.15 fFM - - tFMILH tFMIHL tFMIH tFMI L VFMIAC VFMIDC 0V DVSS Fig. 4-22: Main clock input 4.6.4.3. Reset Input, Test Input Symbol VIL VIH Parameter Input Low Voltage Input High Voltage Pin Name RESQ TEST Min. - 3.0 Typ. - - Max. 1.5 - Unit V V Test Conditions 56 Micronas PRELIMINARY DATA SHEET VDP 31xxB 4.6.4.4. I2C Bus Interface Symbol VIL VIH VOL VIH tF tR fSCL tLOW tHIGH tSU Data tHD Data Parameter Input Low Voltage Input High Voltage Output Low Voltage Pin Name SDA, SCL Min. - 3.0 - Typ. - - - Max. 1.5 - 0.4 0.6 4 300 300 400 - - - 0.9 Unit V V V V pF ns ns kHz ms ms ns ms CL = 400 pF CL = 400 pF Il = 3 mA Il = 6 mA Test Conditions Input Capacitance Signal Fall Time Signal Rise Time Clock Frequency Low Period of SCL High Period of SCL Data Set Up Time to SCL high DATA Hold Time to SCL low SDA SCL - - - 0 1.3 0.6 100 0 - - - - - - - - 4.6.4.5. IO Port Expander Symbol VIL VIH VOL VOH tOD IOL Parameter Input Low Voltage Input High Voltage Output Low Voltage Pin Name PORT[6:0] Min. - 1.5 - Typ. - - 0.2 Max. 0.8 - 0.4 Unit V V V IOL = 1.6 mA, strength 6 -IOL = 1.6mA, strength 6 CLOAD = 70pF driver imp. = 0 Test Conditions Output High Voltage VSUPD - 0.4 - -10 - VSUPD 35 10 V Output Transition Time Output Current - - ns mA 4.6.4.6. Analog Video Inputs Symbol VVIN Parameter Analog Input Voltage Pin Name VIN1 VIN2 VIN3 VIN4 CIN VIN1 VIN2 VIN3 VIN4 CIN Min. 0 Typ. - Max. 3.5 Unit V Test Conditions CCP Input Coupling Capacitor Video Inputs - 680 - nF CCP Input Coupling Capacitor Chroma Input - 1 - nF Micronas 57 VDP 31xxB 4.6.4.7. Analog Front-End and ADCs Symbol VVRT Luma - Path RVIN CVIN VVIN VVIN AGC DNLAGC VVINCL QCL ICL-LSB DNLICL CICL Chroma - Path RCIN VCIN VCINDC Input Resistance SVHS Chroma Full Scale Input Voltage, Chroma Input Bias Level, SVHS Chroma Binary Code for Open Chroma Input Dynamic Characteristics for all Video Paths (Luma + Chroma) BW XTALK THD Bandwidth Crosstalk, any Two Video Inputs Total Harmonic Distortion VIN1 VIN2 VIN3 VIN4 CIN 10 12.5 -56 50 MHz dB dB CIN VIN1 1.4 2.0 2.6 kW Input Resistance Input Capacitance Full Scale Input Voltage Full Scale Input Voltage AGC Step Width AGC Differential Non-Linearity Input Clamping Level, CVBS 1.0 VIN1 VIN2 VIN3 VIN4 1 4.5 1.8 0.5 2.0 0.6 0.166 0.5 2.2 0.7 MW pF VPP VPP dB LSB V Parameter Reference Voltage Top Pin Name VRT Min. 2.5 Typ. 2.6 Max. 2.8 Unit V PRELIMINARY DATA SHEET Test Conditions 10 mF/10 nF, 1 GW Probe Code Clamp - DAC = 0 min. AGC Gain max. AGC Gain 6-Bit Resolution = 64 Steps fsig = 1 MHz MHz, i -2 dBr of max. AGC-Gain Binary Level = 64 LSB min. AGC Gain 5 Bit - I-DAC, bipolar VVIN = 1.5 V 15 Clamping DAC Resolution Input Clamping Current per Step Clamping DAC Differential NonLinearity Clamping-Capacity -16 0.7 1.0 15 1.3 0.5 steps mA LSB 220 - nF Coupling-Cap. @ Inputs 1.08 - 1.2 1.5 1.32 - VPP V 128 -2 dBr input signal level 1 MHz, -2 dBr signal level 1 MHz, 5 harmonics, -2 dBr signal level 1 MHz, all outputs, -2 dBr signal level Code Density, DC-ramp DC ramp SINAD Signal to Noise and Distortion Ratio Integral Non-Linearity, Differential Non-Linearity Differential Gain Differential Phase 45 1 0.8 3 1.5 dB INL DNL DG DP LSB LSB % deg -12 dBr, 4.4 MHz signal on DCramp 58 Micronas PRELIMINARY DATA SHEET VDP 31xxB Analog Front-End and ADCs, continued Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions Analog Video Output VOUT AGCVOUT DNLAGC VOUTDC BW Output Voltage AGC Step Width, VOUT AGC Differential Non-Linearity DC-Level VOUT Bandwidth VOUT Total Harmonic Distortion 1 10 VOUT 1.7 2.0 1.333 0.5 2.3 VPP dB LSB V MHz clamped to back porch Input: -2 dBr of main ADC range, CL 10 pF Input: -2 dBr of main ADC range, CL 10 pF 1 MHz, 5 Harmonics VVIN = 1 VPP, AGC = 0 dB 3 Bit Resolution = 7 Steps 3 MSB's of main AGC THD -45 -40 dB CLVOUT ILVOUT Load Capacitance Output Current - - - - 10 0.1 pF mA 4.6.4.8. Picture Bus Input (see Fig. 4-23) Symbol VIL VIH tIS tIH Parameter Input Low Voltage Input High Voltage Input Setup Time Input Hold Time Pin Name PR[2:0] COLCOL OR[4:0] Min. - 1.5 7 5 Typ. - - - - Max. 0.8 - - - Unit V V ns ns Test Conditions Main Clock tIS Data Inputs tIH Fig. 4-23: Picture bus input timing Micronas 59 VDP 31xxB 4.6.4.9. INTLC, Front Sync Output Symbol VOL VOH tOH tOD IOL Parameter Output Low Voltage Pin Name INTLC FSY Min. - Typ. 0.2 Max. 0.4 PRELIMINARY DATA SHEET Unit V Test Conditions IOL = 1.6 mA, strength 6 -IOL = 1.6mA, strength 6 CLOAD = 70pF CLOAD = 70pF driver imp. = 0 Output High Voltage VSUPD - 0.4 6 - -10 - VSUPD V Output Hold Time Output Delay Time Output Current 14 - - 35 10 ns ns mA 4.6.4.10. Main Sync Output Symbol VOL VOH tOH tOD IOL Parameter Output Low Voltage Pin Name MSY Min. - Typ. 0.2 Max. 0.4 Unit V Test Conditions IOL = 1.6 mA, strength 6 -IOL = 1.6mA, strength 6 CLOAD = 70pF CLOAD = 70pF driver imp. = 0 Output High Voltage VSUPD - 0.4 6 - -10 - VSUPD V Output Hold Time Output Delay Time Output Current 14 - - 35 10 ns ns mA 4.6.4.11. Combined Sync Output Symbol VOL VOH tOT IOL Parameter Output Low Voltage Pin Name CSY Min. - Typ. - Max. 0.4 Unit V Test Conditions IOL = 1.6 mA strength 6 -IOL = 1.6 mA strength 6 CLOAD = 30 pF driver imp. = 0 Output High Voltage VSUPD - 0.4 - -10 - VSUPD 20 10 V Output Transition Time Output Current 10 - ns mA 60 Micronas PRELIMINARY DATA SHEET VDP 31xxB 4.6.4.12. Horizontal Flyback Input Symbol VIL VIH VIHST PSRRHF PSRRMF PSRRLF tPID Parameter Input Low Voltage Input High Voltage Input Hysteresis Power Supply Rejection Ratio of Trigger Level Power Supply Rejection Ratio of Trigger Level Power Supply Rejection Ratio of Trigger Level Internal Delay Pin Name HFLB Min. - 2.6 0.1 0 Typ. - - - Max. 1.8 - - Unit V V V dB f = 20 MHz Test Conditions -20 dB f < 15 kHz -40 dB f < 100 Hz 12 ns slew rate 500 mV/ns swing 1 VPP 4.6.4.13. Horizontal Drive Output Symbol VOL VOH tOF IOL Parameter Output Low Voltage Output High Voltage (Open Drain Stage) Output Fall Time Output Low Current Pin Name HOUT Min. - - Typ. - - Max. 0.4 5 Unit V V Test Conditions IOL = 10 mA external pull-up resistor - - 8 - 20 10 ns mA CLOAD = 30pF 4.6.4.14. Vertical Protection Input Symbol VIL VIH VIHST Parameter Input Low Voltage Input High Voltage Input Hysteresis Pin Name VPROT Min. - 2.6 0.1 Typ. - - - Max. 1.8 - - Unit V V V Test Conditions 4.6.4.15. Vertical Safety Input Symbol VILA VIHA VILB VIHB VIHST tPID Parameter Input Low Voltage A Input High Voltage A Input Low Voltage B Input High Voltage B Input Hysteresis A and B Internal Delay Pin Name SAFETY Min. - 2.6 - 3.9 0.1 Typ. - - - - - Max. 1.8 - 3.1 - - 100 Unit V V V V V ns Test Conditions Micronas 61 VDP 31xxB PRELIMINARY DATA SHEET 4.6.4.16. Vertical and East/West Drive Output Symbol VOL VOH Idacn PSRR Parameter Output Voltage LOW Pin Name EW VERT 2.82 Min. Typ. 0 Max. Unit V Test Conditions Rload = 6800 Rxref = 10 kW Rload = 6800 Rxref = 10 kW Vo = 0 V Rxref = 10 kW Output Voltage HIGH 3 3.2 V A Full scale DAC Output Current Power Supply Rejection Ratio 415 440 465 20 - - dB 4.6.4.17. Sense A/D Converter Input Symbol VI VI255 C0 Parameter Input Voltage Range Input Voltage for code 255 Pin Name SENSE Min. 0 1.4 Typ. - 1.54 Max. Vsup 1.7 Unit V V Read cutoff blue register Offset check, read cutoff blue register Test Conditions Digital Output for zero Input 16 LSB RI Input Impedance 1 - - MW Range Switch Outputs RON IMax ILEAK CIN Output On Resistance Maximum Current Leakage Current Input Capacitance RSW1 RSW2 - - - - - - - - 50 15 600 4 W mA nA pF RSW High Impedance IOL = 10 mA 4.6.4.18. Analog RGB and FB Inputs (continued on next page) Symbol VRGBIN VRGBIN VRGBIN Parameter External RGB Inputs Voltage Range nominal RGB Input Voltage peak-to-peak RGB Inputs Voltage for Maximum Output Current RGB Inputs Voltage for Maximum Output Current RGB Inputs Voltage for Maximum Output Current Pin Name RIN GIN BIN RIN2 GIN2 BIN2 Min. -0.3 Typ. - Max. 1.1 Unit V SCART Spec: 0.7 V 3 dB Test Conditions 0.5 0.7 1.0 VPP 0.44 Contrast setting: 511 0.7 Contrast setting: 323 1.1 Contrast setting: 204 62 Micronas PRELIMINARY DATA SHEET VDP 31xxB Analog RGB and FB Inputs, continued Symbol CRGBIN Parameter External RGB Input Coupling Capacitor Clamp Pulse Width CIN IIL VCLIP VCLAMP VINOFF Input Capacitance Input Leakage Current Pin Name RIN GIN BIN RIN2 GIN2 BIN2 Min. Typ. 15 Max. Unit nF s - - 13 0.5 pF mA Clamping OFF, VIN -0.3..3 V Test Conditions 3.1 - -0.5 RGB Input Voltage for Clipping Current Clamp Level at Input Offset Level at Input 40 -10 2 V 60 80 10 mV mV Clamping ON Extrapolated from VIN = 100 mV and 200 mV Extrapolated from VIN = 100 mV and 200 mV VINOFF RCLAMP VFBLOFF Offset Level Match at Input -10 10 mV V V Clamping-ON-Resistance FBLIN Low Level FBLIN High Level Fast Blanking Trigger Level typical Delay Fast Blanking to RGBOUT from midst of FBLIN-transition to 90% of RGBOUT-transition FBLIN FBLIN2 - 0.9 140 - - 0.7 - 0.5 - VFBLON VFBLTRIG tPID 8 15 ns Internal RGB = 3.75 mA Full Scale Int. Brightness = 0 External Brightness = 1.5 mA (Full Scale) RGBin = 0 VFBLOFF = 0.4 V VFBLON = 1.0 V Rise and fall time = 2 ns Difference of Internal Delay to External RGBin Delay Switch-Over-Glitch -5 +5 ns 0.5 pAs Switch from 3.75 mA (int) to 1.5 mA (ext) 4.6.4.19. Half Contrast Switch Input Symbol VIL VIH tHCS Parameter Input Low Voltage Input High Voltage Delay HCS to RGBOUT from 50% of HCS-transition to 90% of RGBOUT-transition Pin Name HCS Min. - 1.5 Typ. - - 80 Max. 0.8 - 120 Unit V V ns Internal RGB = 3.75 mA VHCSL = 0.4 V VHCSH = 1.0 V Rise and fall time = 2 ns Test Conditions Micronas 63 VDP 31xxB 4.6.4.20. Analog RGB Outputs, D/A Converters Symbol Parameter Pin Name Min. Typ. Max. PRELIMINARY DATA SHEET Unit Test Conditions Internal RGB Signal D/A Converter Characteristics Resolution IOUT IOUTHC Full Scale Output Current Half Contrast Output Current ROUT GOUT BOUT - 3.6 1.74 10 3.75 1.87 - 3.9 2.0 bit mA mA Rref = 10 k Rref = 10 k, IOUT = 3.75 mA Differential Nonlinearity Integral Nonlinearity Glitch Pulse Charge 0.5 0.5 1 LSB LSB pAs Ramp signal, 25 output termination 10% to 90%, 90% to 10% 60% to 90% IOUT = 3.75mA 90% to 60% IOUT = 3.75mA 2/2.5 MHz full scale Signal: 1MHz full scale Bandwidth: 10MHz tT tRHC tFHC Rise and Fall Time Half Contrast Rise Time Half Contrast Fall Time Intermodulation Signal to Noise +50 3 50 25 75 40 -50 ns ns ns dB dB DRGB DRGBHC Matching R-G, R-B, G-B Half Contrast Matching R-G, R-B, G-B R/B/G Crosstalk one channel talks two channels talk RGB Input Crosstalk from external RGB one channel talks two channels talk three channels talk -2 -5 2 5 % % -46 dB Passive channel: IOUT =1.88 mA Crosstalk-Signal: 1.25 MHz, 3.75 3 75 mAPP -50 -50 -50 dB dB dB Internal RGB Brightness D/A Converter Characteristics Resolution IBR IBR IBR IBR IBR IBR Full Scale Output Current relative Full Scale Output Current absolute differential nonlinearity integral nonlinearity Match R-G, R-B, G-B Match to digital RGB R-R, G-G, B-B -2 -2 ROUT GOUT BOUT 9 39.2 40 40.8 bits % Ref to max. digital RGB 1.5 mA 0.5 1 2 2 LSB LSB % % External RGB Voltage/Current Converter Characteristics Resolution IEXOUT Full Scale Output Current relative Full Scale Output Current absolute ROUT GOUT BOUT 9 96 100 104 bits % Ref. to max. Digital RGB VIN = 0.7 VPP, contrast = 323 Same as Digital RGB 3.75 mA 64 Micronas PRELIMINARY DATA SHEET VDP 31xxB Analog RGB Outputs, D/A Converters, continued Symbol CR Parameter Contrast Adjust Range Gain Match R-G, R-B, G-B Pin Name ROUT GOUT BOUT Min. Typ. 16:511 -2 2 % Measured at RGB Outputs VIN = 0.7 V, contrast = 323 Measured at RGB Outputs VIN = 0.7 V, contrast = 323 Passive channel: VIN = 0.7V, contrast = 323 Crosstalk signal: 1.25 MHz, 3.75 mAPP Max. Unit Test Conditions Gain Match to RGB-DACs R-R, G-G, B-B R/B/G Input Crosstalk one channel talks two channels talk RGB Input Crosstalk from Internal RGB one channel talks two channels talk three channels talk RGB Input Noise and Distortion -3 3 % -46 dB -50 dB -50 dB VIN = 0.7 VPP at 1 MHz contrast = 323 Bandwidth: 10 MHz VIN = 0.7 VPP, contrast = 323 Input signal 1 MHz Input signal 6 MHz VIN = 0.7 VPP contrast = 323 VIN = 0.44 V RGB Input Bandwidth -3dB 10 15 - MHz RGB Input THD -50 -40 dB dB Differential Nonlinearity of Contrast Adjust Integral nonlinearity of Contrast Adjust VRGBO RGB Output Voltage RGB Output Load Resistance VOUTC RGB Output Compliance -1.5 -1.3 -1.0 1.0 LSB 7 LSB 0.3 100 -1.2 V V Referred to VSUPO Ref. to VSUPO Ref. to VSUPO Sum of max. Current of RGB-DACs and max. Current of Int. Brightness DACs is 2% degraded External RGB Brightness D/A Converter Characteristics Resolution IEXBR Full Scale Output Current relative Full Scale Output Current absolute Differential Nonlinearity Integral Nonlinearity Matching R-G, R-B, G-B Matching to digital RGB R-R, G-G, B-B -2 -2 ROUT GOUT BOUT 9 39.2 40 40.8 bits % Ref to max. digital RGB 1.5 mA 0.5 1 2 2 LSB LSB % % Micronas 65 VDP 31xxB Analog RGB Outputs, D/A Converters, continued Symbol Parameter Pin Name Min. Typ. Max. PRELIMINARY DATA SHEET Unit Test Conditions RGB Output Cutoff D/A Converter Characteristics Resolution ICUT ICUT ICUT ICUT ICUT Full Scale Output Current relative Full Scale Output Current absolute Differential nonlinearity Integral nonlinearity Match to digital RGB R-R, G-G, B-B -2 ROUT GOUT BOUT 9 58.8 60 61.2 bits % Ref to max. digital RGB 2.25 mA 0.5 1 2 LSB LSB % RGB Output Ultrablack D/A Converter Characteristics Resolution IUB Full Scale Output Current relative Full Scale Output Current absolute Match to digital RGB R-R, G-G, B-B *2 ROUT GOUT BOUT 1 19.6 20 20.4 bits % Ref to max. digital RGB 0.75 mA 2 % 4.6.4.21. DAC Reference, Beam Current Safety Symbol VDACREF Parameter DAC-Reference Voltage Pin Name VRD/BCS Min. 2.38 Typ. 2.50 Max. 2.67 Unit V Test Conditions DAC-Reference Output resistance VXREF DAC-Reference Voltage Bias Current Generation VRD/BCS 18 25 32 kW XREF 2.25 2.34 2.43 V Rref = 10 k, 4.6.4.22. Scan Velocity Modulation Output Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions SVM D/A Converter Characteristics Resolution IOUT IOUT IOUT IOUT Full Scale Output Current Differential Nonlinearity Integral Nonlinearity Glitch Pulse Charge 0.5 SVMOUT 1.55 8 1.875 2.25 0.5 1 bit mA LSB LSB pAs Ramp, output line is terminated on both ends with 50 Ohms 10% to 90%, 90% to 10% IOUT Rise and Fall Time 3 nsec 66 Micronas PRELIMINARY DATA SHEET VDP 31xxB 5. Application Circuit Micronas 67 VDP 31xxB PRELIMINARY DATA SHEET 68 Micronas PRELIMINARY DATA SHEET VDP 31xxB Micronas 69 VDP 31xxB PRELIMINARY DATA SHEET 70 Micronas PRELIMINARY DATA SHEET VDP 31xxB Micronas 71 VDP 31xxB 6. Data Sheet History 1. Preliminary data sheet: "VDP 31xxB Video Processor Family", Edition May 15, 1997, 6251-437-1PD. First release of the preliminary data sheet. 2. Preliminary data sheet: "VDP 31xxB Video Processor Family", Edition Sept. 25, 1998, 6251-437-2PD. Second release of the preliminary data sheet. Major changes: - section 4.1.: package outline dimensions changed - section 4.6.: missing values have been defined - section 5.: application circuit diagram corrected PRELIMINARY DATA SHEET Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-437-2PD All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH. 72 Micronas |
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